fsel can take a different FP type for the comparison and for the result. As such
split the FSEL family into 4 things instead of just two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 4721d3e..3a92d08 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -752,18 +752,21 @@
CodeGenMap[Op.getValue(1)] = Result.getValue(1);
return SDOperand(Result.Val, Op.ResNo);
}
- case PPCISD::FSEL:
- if (N->getValueType(0) == MVT::f32)
- CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32,
- Select(N->getOperand(0)),
- Select(N->getOperand(1)),
- Select(N->getOperand(2)));
- else
- CurDAG->SelectNodeTo(N, PPC::FSELD, MVT::f64,
- Select(N->getOperand(0)),
- Select(N->getOperand(1)),
- Select(N->getOperand(2)));
+ case PPCISD::FSEL: {
+ unsigned Opc;
+ if (N->getValueType(0) == MVT::f32) {
+ Opc = N->getOperand(0).getValueType() == MVT::f32 ?
+ PPC::FSELSS : PPC::FSELSD;
+ } else {
+ Opc = N->getOperand(0).getValueType() == MVT::f64 ?
+ PPC::FSELDD : PPC::FSELDS;
+ }
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
+ Select(N->getOperand(0)),
+ Select(N->getOperand(1)),
+ Select(N->getOperand(2)));
return SDOperand(N, 0);
+ }
case PPCISD::FCFID:
CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
Select(N->getOperand(0)));
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 0571049..729ffb5 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -816,9 +816,12 @@
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));
if (N.getOperand(0).getValueType() == MVT::f32)
- BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ Opc = N.getOperand(0).getValueType() == MVT::f32 ?
+ PPC::FSELSS : PPC::FSELSD;
else
- BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ Opc = N.getOperand(0).getValueType() == MVT::f64 ?
+ PPC::FSELDD : PPC::FSELDS;
+ BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result;
case PPCISD::FCFID:
Tmp1 = SelectExpr(N.getOperand(0));
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index bc4278c..c4bb8a6 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -791,15 +791,24 @@
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fnmsubs $FRT, $FRA, $FRC, $FRB",
[]>;
-// FSEL is artificially split into 4 and 8-byte forms.
-def FSELD : AForm_1<63, 23,
- (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB",
- []>;
-def FSELS : AForm_1<63, 23,
- (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB",
- []>;
+// FSEL is artificially split into 4 and 8-byte forms for the comparison type
+// and 4/8 byte forms for the result and operand type..
+def FSELDD : AForm_1<63, 23,
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
+def FSELSS : AForm_1<63, 23,
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
+def FSELDS : AForm_1<63, 23, // result Double, comparison Single
+ (ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
+def FSELSD : AForm_1<63, 23, // result Single, comparison Double
+ (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
def FADD : AForm_2<63, 21,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fadd $FRT, $FRA, $FRB",