commit 87076054e6292c2018676a175e05359c28881e10
author Andrew Lenharth <andrewl@lenharth.org> Mon Jan 23 21:23:26 2006 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Mon Jan 23 21:23:26 2006 +0000
tree 68af510c031c9f07511b6d3c293bc84824745faa
parent 167bc6ee7afda12321f543a42e4a8e5b4e864804

fix up more lsmark stuff


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25550 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelLowering.cpp

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index f75009c..79d09c0 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -73,6 +73,14 @@
     setOperationAction(ISD::LOAD, MVT::i64, Custom);
     setOperationAction(ISD::LOAD, MVT::f64, Custom);
     setOperationAction(ISD::LOAD, MVT::f32, Custom);
+
+    setOperationAction(ISD::ZEXTLOAD, MVT::i8,  Custom);
+    setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
+    setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
+
+    setOperationAction(ISD::EXTLOAD, MVT::i8,  Custom);
+    setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
+    setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
   }
 
   setOperationAction(ISD::FREM, MVT::f32, Expand);
@@ -578,6 +586,7 @@
   case ISD::LOAD:
   case ISD::SEXTLOAD:
   case ISD::ZEXTLOAD:
+  case ISD::EXTLOAD:
     {
       SDOperand Chain   = Op.getOperand(0);
       SDOperand Address = Op.getOperand(1);
@@ -612,13 +621,13 @@
       VTS.push_back(Op.Val->getValueType(0));
       VTS.push_back(MVT::Other);
       std::vector<SDOperand> ARGS;
+      ARGS.push_back(Chain);
       ARGS.push_back(Zero);
       ARGS.push_back(Address);
       ARGS.push_back(DAG.getConstant(i, MVT::i64));
       ARGS.push_back(DAG.getConstant(j, MVT::i64));
       ARGS.push_back(DAG.getConstant(k, MVT::i64));
       ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
-      ARGS.push_back(Chain);
       return DAG.getNode(Opc, VTS, ARGS);
     }