Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3e2ab2c..31b2a47 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2294,9 +2294,16 @@
// NOTE: we could fall back on load/store here too for targets without
// SAR. However, it is doubtful that any exist.
EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
- unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
+ EVT VT = Node->getValueType(0);
+ EVT ShiftAmountTy = TLI.getShiftAmountTy();
+ if (ExtraVT.isVector()) ExtraVT = ExtraVT.getVectorElementType();
+ if (VT.isVector()) {
+ ShiftAmountTy = VT;
+ VT = VT.getVectorElementType();
+ }
+ unsigned BitsDiff = VT.getSizeInBits() -
ExtraVT.getSizeInBits();
- SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
+ SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
Node->getOperand(0), ShiftCst);
Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);