Allows instructions which no explicit operands. e.g. X86 RET which has but
an implicit flag operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24916 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index be8fb75..140c8f2 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -1124,23 +1124,22 @@
std::vector<Record*> Operands;
CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
-
- // Doesn't even define a result?
- if (InstInfo.OperandList.size() == 0)
- continue;
+ // Note: Removed if (InstInfo.OperandList.size() == 0) continue;
+ // It's possible for some instruction, e.g. RET for X86 that only has an
+ // implicit flag operand.
// FIXME: temporary hack...
if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
InstInfo.isStore) {
// These produce no results
- for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
+ for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
Operands.push_back(InstInfo.OperandList[j].Rec);
} else {
// Assume the first operand is the result.
Results.push_back(InstInfo.OperandList[0].Rec);
// The rest are inputs.
- for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
+ for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
Operands.push_back(InstInfo.OperandList[j].Rec);
}