minor tidying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100725 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 583161f..d783dd0 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5326,6 +5326,7 @@
// error.
if (OpInfo.hasMatchingInput()) {
SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
+
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
if ((OpInfo.ConstraintVT.isInteger() !=
Input.ConstraintVT.isInteger()) ||
@@ -5539,10 +5540,9 @@
std::vector<SDValue> Ops;
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
hasMemory, Ops, DAG);
- if (Ops.empty()) {
+ if (Ops.empty())
report_fatal_error("Invalid operand for inline asm"
" constraint '" + OpInfo.ConstraintCode + "'!");
- }
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType =
@@ -5574,10 +5574,9 @@
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty() ||
- !OpInfo.AssignedRegs.areValueTypesLegal()) {
+ !OpInfo.AssignedRegs.areValueTypesLegal())
report_fatal_error("Couldn't allocate input reg for"
" constraint '"+ OpInfo.ConstraintCode +"'!");
- }
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
Chain, &Flag);