commit 880d0f6018b6928bdcad291be60c801238619955
author Bill Wendling <isanbard@gmail.com> Tue Mar 04 23:13:51 2008 +0000
committer Bill Wendling <isanbard@gmail.com> Tue Mar 04 23:13:51 2008 +0000
tree ace3a39b443f41b5e76ab98ef08c1b063cfc2693
parent 6494768ffcdf75e6e69a7955282db9ab9ab2e6fb

Use a command-line option to turn register scavenging on/off for PPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index afaf8da..d8f6015 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -19,8 +19,11 @@
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
+extern cl::opt<bool> EnablePPCRS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
+
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
@@ -320,8 +323,7 @@
 static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
                                 unsigned SrcReg, bool isKill, int FrameIdx,
                                 const TargetRegisterClass *RC,
-                                SmallVectorImpl<MachineInstr*> &NewMIs,
-                                bool isPPC64/*FIXME (64-bit): Remove.*/) {
+                                SmallVectorImpl<MachineInstr*> &NewMIs) {
   if (RC == PPC::GPRCRegisterClass) {
     if (SrcReg != PPC::LR) {
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
@@ -353,7 +355,7 @@
     NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
                                 .addReg(SrcReg, false, false, isKill), FrameIdx));
   } else if (RC == PPC::CRRCRegisterClass) {
-    if (!isPPC64) {             // FIXME (64-bit): Enable
+    if (EnablePPCRS) {  // FIXME (64-bit): Enable
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
                                          .addReg(SrcReg, false, false, isKill),
 					 FrameIdx));
@@ -402,8 +404,7 @@
                                   const TargetRegisterClass *RC) const {
   SmallVector<MachineInstr*, 4> NewMIs;
 
-  if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs,
-                 TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) {
+  if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
     PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
     FuncInfo->setSpillsCR();
   }
@@ -418,8 +419,8 @@
                                   const TargetRegisterClass *RC,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
   if (Addr[0].isFrameIndex()) {
-    if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs,
-                 TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) {
+    if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(),
+                            RC, NewMIs)) {
       PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
       FuncInfo->setSpillsCR();
     }