diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 08e1898..b620589 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -437,8 +437,8 @@
     //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
       SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
                                         DAG.getConstant(8*6, MVT::i64));
-      SDOperand CC = DAG.getSetCC(ISD::SETLT, MVT::i64,
-                                  Offset, DAG.getConstant(8*6, MVT::i64));
+      SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
+                                  DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
       DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
   }
 
@@ -896,15 +896,14 @@
 
 bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
 {
-  SDNode *Node = N.Val;
+  SDNode *SetCC = N.Val;
   unsigned Opc, Tmp1, Tmp2, Tmp3;
-  SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node);
-
+  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
   bool rev = false;
   bool inv = false;
 
-  switch (SetCC->getCondition()) {
-  default: Node->dump(); assert(0 && "Unknown FP comparison!");
+  switch (CC) {
+  default: SetCC->dump(); assert(0 && "Unknown FP comparison!");
   case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
   case ISD::SETLT: Opc = Alpha::CMPTLT; break;
   case ISD::SETLE: Opc = Alpha::CMPTLE; break;
@@ -978,16 +977,14 @@
 
   if (CC.getOpcode() == ISD::SETCC)
   {
-    SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
-    if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
+    ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
+    if (MVT::isInteger(CC.getOperand(0).getValueType())) {
       //Dropping the CC is only useful if we are comparing to 0
-      bool RightZero = SetCC->getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0;
+      bool RightZero = CC.getOperand(1).getOpcode() == ISD::Constant &&
+        cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0;
       bool isNE = false;
 
       //Fix up CC
-      ISD::CondCode cCode= SetCC->getCondition();
-
       if(cCode == ISD::SETNE)
         isNE = true;
 
@@ -1006,7 +1003,7 @@
         case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
         case ISD::SETNE:  Opc = Alpha::BNE; break;
         }
-        unsigned Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
+        unsigned Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
         BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
         return;
       } else {
@@ -1029,26 +1026,26 @@
       unsigned Tmp3;
 
       ConstantFPSDNode *CN;
-      if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
+      if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
           && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-        Tmp3 = SelectExpr(SetCC->getOperand(0));
-      else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
+        Tmp3 = SelectExpr(CC.getOperand(0));
+      else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
           && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
       {
-        Tmp3 = SelectExpr(SetCC->getOperand(1));
+        Tmp3 = SelectExpr(CC.getOperand(1));
         invTest = true;
       }
       else
       {
-        unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
-        unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
-        bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
+        unsigned Tmp1 = SelectExpr(CC.getOperand(0));
+        unsigned Tmp2 = SelectExpr(CC.getOperand(1));
+        bool isD = CC.getOperand(0).getValueType() == MVT::f64;
         Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
         BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
           .addReg(Tmp1).addReg(Tmp2);
       }
 
-      switch (SetCC->getCondition()) {
+      switch (cCode) {
       default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
       case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
       case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
@@ -1533,71 +1530,70 @@
 
   case ISD::SETCC:
     {
-      if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-        if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
-          bool isConst = false;
-          int dir;
+      ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(2))->get();
+      if (MVT::isInteger(N.getOperand(0).getValueType())) {
+        bool isConst = false;
+        int dir;
 
-          //Tmp1 = SelectExpr(N.getOperand(0));
-          if(N.getOperand(1).getOpcode() == ISD::Constant &&
-             cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
-            isConst = true;
+        //Tmp1 = SelectExpr(N.getOperand(0));
+        if(N.getOperand(1).getOpcode() == ISD::Constant &&
+           cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
+          isConst = true;
 
-          switch (SetCC->getCondition()) {
-          default: Node->dump(); assert(0 && "Unknown integer comparison!");
-          case ISD::SETEQ:
-            Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
-          case ISD::SETLT:
-            Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
-          case ISD::SETLE:
-            Opc = isConst ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
-          case ISD::SETGT: Opc = Alpha::CMPLT; dir = 2; break;
-          case ISD::SETGE: Opc = Alpha::CMPLE; dir = 2; break;
-          case ISD::SETULT:
-            Opc = isConst ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
-          case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 2; break;
-          case ISD::SETULE:
-            Opc = isConst ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
-          case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 2; break;
-          case ISD::SETNE: {//Handle this one special
-            //std::cerr << "Alpha does not have a setne.\n";
-            //abort();
-            Tmp1 = SelectExpr(N.getOperand(0));
+        switch (CC) {
+        default: Node->dump(); assert(0 && "Unknown integer comparison!");
+        case ISD::SETEQ:
+          Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
+        case ISD::SETLT:
+          Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
+        case ISD::SETLE:
+          Opc = isConst ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
+        case ISD::SETGT: Opc = Alpha::CMPLT; dir = 2; break;
+        case ISD::SETGE: Opc = Alpha::CMPLE; dir = 2; break;
+        case ISD::SETULT:
+          Opc = isConst ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
+        case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 2; break;
+        case ISD::SETULE:
+          Opc = isConst ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
+        case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 2; break;
+        case ISD::SETNE: {//Handle this one special
+          //std::cerr << "Alpha does not have a setne.\n";
+          //abort();
+          Tmp1 = SelectExpr(N.getOperand(0));
+          Tmp2 = SelectExpr(N.getOperand(1));
+          Tmp3 = MakeReg(MVT::i64);
+          BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+          //Remeber we have the Inv for this CC
+          CCInvMap[N] = Tmp3;
+          //and invert
+          BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
+          return Result;
+        }
+        }
+        if (dir == 1) {
+          Tmp1 = SelectExpr(N.getOperand(0));
+          if (isConst) {
+            Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
+            BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
+          } else {
             Tmp2 = SelectExpr(N.getOperand(1));
-            Tmp3 = MakeReg(MVT::i64);
-            BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
-            //Remeber we have the Inv for this CC
-            CCInvMap[N] = Tmp3;
-            //and invert
-            BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
-            return Result;
-          }
-          }
-          if (dir == 1) {
-            Tmp1 = SelectExpr(N.getOperand(0));
-            if (isConst) {
-              Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
-              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
-            } else {
-              Tmp2 = SelectExpr(N.getOperand(1));
-              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-            }
-          } else { //if (dir == 2) {
-            Tmp1 = SelectExpr(N.getOperand(1));
-            Tmp2 = SelectExpr(N.getOperand(0));
             BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
           }
-        } else {
-          //do the comparison
-          Tmp1 = MakeReg(MVT::f64);
-          bool inv = SelectFPSetCC(N, Tmp1);
-
-          //now arrange for Result (int) to have a 1 or 0
-          Tmp2 = MakeReg(MVT::i64);
-          BuildMI(BB, Alpha::ADDQi, 2, Tmp2).addReg(Alpha::R31).addImm(1);
-          Opc = inv?Alpha::CMOVNEi_FP:Alpha::CMOVEQi_FP;
-          BuildMI(BB, Opc, 3, Result).addReg(Tmp2).addImm(0).addReg(Tmp1);
+        } else { //if (dir == 2) {
+          Tmp1 = SelectExpr(N.getOperand(1));
+          Tmp2 = SelectExpr(N.getOperand(0));
+          BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
         }
+      } else {
+        //do the comparison
+        Tmp1 = MakeReg(MVT::f64);
+        bool inv = SelectFPSetCC(N, Tmp1);
+
+        //now arrange for Result (int) to have a 1 or 0
+        Tmp2 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::ADDQi, 2, Tmp2).addReg(Alpha::R31).addImm(1);
+        Opc = inv?Alpha::CMOVNEi_FP:Alpha::CMOVEQi_FP;
+        BuildMI(BB, Opc, 3, Result).addReg(Tmp2).addImm(0).addReg(Tmp1);
       }
       return Result;
     }
@@ -1927,10 +1923,10 @@
       unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
 
       SDOperand CC = N.getOperand(0);
-      SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
 
-      if (SetCC && !MVT::isInteger(SetCC->getOperand(0).getValueType()))
-      { //FP Setcc -> Select yay!
+      if (CC.getOpcode() == ISD::SETCC &&
+          !MVT::isInteger(CC.getOperand(0).getValueType())) {
+        //FP Setcc -> Select yay!
 
 
         //for a cmp b: c = a - b;
@@ -1942,26 +1938,26 @@
         unsigned Tmp3;
 
         ConstantFPSDNode *CN;
-        if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
+        if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
             && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-          Tmp3 = SelectExpr(SetCC->getOperand(0));
-        else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
+          Tmp3 = SelectExpr(CC.getOperand(0));
+        else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
                  && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
         {
-          Tmp3 = SelectExpr(SetCC->getOperand(1));
+          Tmp3 = SelectExpr(CC.getOperand(1));
           invTest = true;
         }
         else
         {
-          unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
-          unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
-          bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
+          unsigned Tmp1 = SelectExpr(CC.getOperand(0));
+          unsigned Tmp2 = SelectExpr(CC.getOperand(1));
+          bool isD = CC.getOperand(0).getValueType() == MVT::f64;
           Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
           BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
             .addReg(Tmp1).addReg(Tmp2);
         }
 
-        switch (SetCC->getCondition()) {
+        switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
         default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
         case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
         case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
@@ -1996,10 +1992,9 @@
       //BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
 
       SDOperand CC = N.getOperand(0);
-      SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
 
       if (CC.getOpcode() == ISD::SETCC &&
-          !MVT::isInteger(SetCC->getOperand(0).getValueType()))
+          !MVT::isInteger(CC.getOperand(0).getValueType()))
       { //FP Setcc -> Int Select
         Tmp1 = MakeReg(MVT::f64);
         Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
@@ -2012,15 +2007,15 @@
       if (CC.getOpcode() == ISD::SETCC) {
         //Int SetCC -> Select
         //Dropping the CC is only useful if we are comparing to 0
-        if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
-            cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0))
+        if((CC.getOperand(1).getOpcode() == ISD::Constant &&
+            cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0))
         {
           //figure out a few things
           bool useImm = N.getOperand(2).getOpcode() == ISD::Constant &&
             cast<ConstantSDNode>(N.getOperand(2))->getValue() <= 255;
 
           //Fix up CC
-          ISD::CondCode cCode= SetCC->getCondition();
+          ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
           if (useImm) //Invert sense to get Imm field right
             cCode = ISD::getSetCCInverse(cCode, true);
 
@@ -2039,7 +2034,7 @@
           case ISD::SETUGE: assert(0 && "unsgined >= 0 is always true"); break;
           case ISD::SETNE:  Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE;    break;
           }
-          Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
+          Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
 
           if (useImm) {
             Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 62b195c..5190165 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -1809,109 +1809,103 @@
 
   case ISD::SETCC: {
     Tmp1 = SelectExpr(N.getOperand(0));
+    ISD::CondCode CC = cast<CondCodeSDNode>(Node->getOperand(2))->get();
+    if (MVT::isInteger(N.getOperand(0).getValueType())) {
 
-    if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-      if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
+      if(ConstantSDNode *CSDN =
+           dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+      // if we are comparing against a constant zero
+      if(CSDN->getValue()==0)
+        Tmp2 = IA64::r0; // then we can just compare against r0
+      else
+        Tmp2 = SelectExpr(N.getOperand(1));
+      } else // not comparing against a constant
+        Tmp2 = SelectExpr(N.getOperand(1));
 
-        if(ConstantSDNode *CSDN =
-             dyn_cast<ConstantSDNode>(N.getOperand(1))) {
-        // if we are comparing against a constant zero
-        if(CSDN->getValue()==0)
-          Tmp2 = IA64::r0; // then we can just compare against r0
+      switch (CC) {
+      default: assert(0 && "Unknown integer comparison!");
+      case ISD::SETEQ:
+        BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETGT:
+        BuildMI(BB, IA64::CMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETGE:
+        BuildMI(BB, IA64::CMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETLT:
+        BuildMI(BB, IA64::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETLE:
+        BuildMI(BB, IA64::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETNE:
+        BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETULT:
+        BuildMI(BB, IA64::CMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETUGT:
+        BuildMI(BB, IA64::CMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETULE:
+        BuildMI(BB, IA64::CMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETUGE:
+        BuildMI(BB, IA64::CMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      }
+    } else { // if not integer, should be FP.
+      assert(N.getOperand(0).getValueType() != MVT::f32 &&
+          "error: SETCC should have had incoming f32 promoted to f64!\n");
+
+      if(ConstantFPSDNode *CFPSDN =
+           dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
+
+        // if we are comparing against a constant +0.0 or +1.0
+        if(CFPSDN->isExactlyValue(+0.0))
+          Tmp2 = IA64::F0; // then we can just compare against f0
+        else if(CFPSDN->isExactlyValue(+1.0))
+          Tmp2 = IA64::F1; // or f1
         else
           Tmp2 = SelectExpr(N.getOperand(1));
-        } else // not comparing against a constant
-          Tmp2 = SelectExpr(N.getOperand(1));
+      } else // not comparing against a constant
+        Tmp2 = SelectExpr(N.getOperand(1));
 
-        switch (SetCC->getCondition()) {
-        default: assert(0 && "Unknown integer comparison!");
-        case ISD::SETEQ:
-          BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETGT:
-          BuildMI(BB, IA64::CMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETGE:
-          BuildMI(BB, IA64::CMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETLT:
-          BuildMI(BB, IA64::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETLE:
-          BuildMI(BB, IA64::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETNE:
-          BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETULT:
-          BuildMI(BB, IA64::CMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETUGT:
-          BuildMI(BB, IA64::CMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETULE:
-          BuildMI(BB, IA64::CMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETUGE:
-          BuildMI(BB, IA64::CMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        }
-      }
-      else { // if not integer, should be FP. FIXME: what about bools? ;)
-        assert(SetCC->getOperand(0).getValueType() != MVT::f32 &&
-            "error: SETCC should have had incoming f32 promoted to f64!\n");
-
-        if(ConstantFPSDNode *CFPSDN =
-             dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
-
-          // if we are comparing against a constant +0.0 or +1.0
-          if(CFPSDN->isExactlyValue(+0.0))
-            Tmp2 = IA64::F0; // then we can just compare against f0
-          else if(CFPSDN->isExactlyValue(+1.0))
-            Tmp2 = IA64::F1; // or f1
-          else
-            Tmp2 = SelectExpr(N.getOperand(1));
-        } else // not comparing against a constant
-          Tmp2 = SelectExpr(N.getOperand(1));
-
-        switch (SetCC->getCondition()) {
-        default: assert(0 && "Unknown FP comparison!");
-        case ISD::SETEQ:
-          BuildMI(BB, IA64::FCMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETGT:
-          BuildMI(BB, IA64::FCMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETGE:
-          BuildMI(BB, IA64::FCMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETLT:
-          BuildMI(BB, IA64::FCMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETLE:
-          BuildMI(BB, IA64::FCMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETNE:
-          BuildMI(BB, IA64::FCMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETULT:
-          BuildMI(BB, IA64::FCMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETUGT:
-          BuildMI(BB, IA64::FCMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETULE:
-          BuildMI(BB, IA64::FCMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        case ISD::SETUGE:
-          BuildMI(BB, IA64::FCMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
-          break;
-        }
+      switch (CC) {
+      default: assert(0 && "Unknown FP comparison!");
+      case ISD::SETEQ:
+        BuildMI(BB, IA64::FCMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETGT:
+        BuildMI(BB, IA64::FCMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETGE:
+        BuildMI(BB, IA64::FCMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETLT:
+        BuildMI(BB, IA64::FCMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETLE:
+        BuildMI(BB, IA64::FCMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETNE:
+        BuildMI(BB, IA64::FCMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETULT:
+        BuildMI(BB, IA64::FCMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETUGT:
+        BuildMI(BB, IA64::FCMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETULE:
+        BuildMI(BB, IA64::FCMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
+      case ISD::SETUGE:
+        BuildMI(BB, IA64::FCMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+        break;
       }
     }
-    else
-      assert(0 && "this setcc not implemented yet");
-
     return Result;
   }
 
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index e5b53f5..eb4410b 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -565,24 +565,23 @@
 
   // If the first operand to the select is a SETCC node, then we can fold it
   // into the branch that selects which value to return.
-  SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
-  if (SetCC && CC.getOpcode() == ISD::SETCC) {
+  if (CC.getOpcode() == ISD::SETCC) {
     bool U;
-    Opc = getBCCForSetCC(SetCC->getCondition(), U);
-    Tmp1 = SelectExpr(SetCC->getOperand(0));
+    Opc = getBCCForSetCC(cast<CondCodeSDNode>(CC.getOperand(2))->get(), U);
+    Tmp1 = SelectExpr(CC.getOperand(0));
 
     // Pass the optional argument U to getImmediateForOpcode for SETCC,
     // so that it knows whether the SETCC immediate range is signed or not.
-    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
+    if (1 == getImmediateForOpcode(CC.getOperand(1), ISD::SETCC,
                                    Tmp2, U)) {
       if (U)
         BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
       else
         BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
     } else {
-      bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
+      bool IsInteger = MVT::isInteger(CC.getOperand(0).getValueType());
       unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
-      Tmp2 = SelectExpr(SetCC->getOperand(1));
+      Tmp2 = SelectExpr(CC.getOperand(1));
       BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
     }
   } else {
@@ -650,21 +649,22 @@
     assert(0 && "Node not handled!\n");
 
   case ISD::SELECT: {
+    SDNode *Cond = N.getOperand(0).Val;
     // Attempt to generate FSEL.  We can do this whenever we have an FP result,
     // and an FP comparison in the SetCC node.
-    SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
-    if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
-        !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
-        SetCC->getCondition() != ISD::SETEQ &&
-        SetCC->getCondition() != ISD::SETNE) {
-      MVT::ValueType VT = SetCC->getOperand(0).getValueType();
-      Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+    if (Cond->getOpcode() == ISD::SETCC &&
+        !MVT::isInteger(N.getOperand(1).getValueType()) &&
+        cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETEQ &&
+        cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETNE) {
+      MVT::ValueType VT = Cond->getOperand(0).getValueType();
+      ISD::CondCode CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
+      Tmp1 = SelectExpr(Cond->getOperand(0));   // Val to compare against
       unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
       unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
 
-      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
+      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Cond->getOperand(1));
       if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
-        switch(SetCC->getCondition()) {
+        switch(CC) {
         default: assert(0 && "Invalid FSEL condition"); abort();
         case ISD::SETULT:
         case ISD::SETLT:
@@ -691,9 +691,9 @@
         }
       } else {
         Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
-        Tmp2 = SelectExpr(SetCC->getOperand(1));
+        Tmp2 = SelectExpr(Cond->getOperand(1));
         Tmp3 =  MakeReg(VT);
-        switch(SetCC->getCondition()) {
+        switch(CC) {
         default: assert(0 && "Invalid FSEL condition"); abort();
         case ISD::SETULT:
         case ISD::SETLT:
@@ -1357,54 +1357,51 @@
     return Result;
   }
 
-  case ISD::SETCC:
-    if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-      Opc = SelectSetCR0(N);
+  case ISD::SETCC: {
+    Opc = SelectSetCR0(N);
 
-      unsigned TrueValue = MakeReg(MVT::i32);
-      BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
-      unsigned FalseValue = MakeReg(MVT::i32);
-      BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
+    unsigned TrueValue = MakeReg(MVT::i32);
+    BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
+    unsigned FalseValue = MakeReg(MVT::i32);
+    BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
 
-      // Create an iterator with which to insert the MBB for copying the false
-      // value and the MBB to hold the PHI instruction for this SetCC.
-      MachineBasicBlock *thisMBB = BB;
-      const BasicBlock *LLVM_BB = BB->getBasicBlock();
-      ilist<MachineBasicBlock>::iterator It = BB;
-      ++It;
+    // Create an iterator with which to insert the MBB for copying the false
+    // value and the MBB to hold the PHI instruction for this SetCC.
+    MachineBasicBlock *thisMBB = BB;
+    const BasicBlock *LLVM_BB = BB->getBasicBlock();
+    ilist<MachineBasicBlock>::iterator It = BB;
+    ++It;
 
-      //  thisMBB:
-      //  ...
-      //   cmpTY cr0, r1, r2
-      //   %TrueValue = li 1
-      //   bCC sinkMBB
-      MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
-      MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
-      BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
-      MachineFunction *F = BB->getParent();
-      F->getBasicBlockList().insert(It, copy0MBB);
-      F->getBasicBlockList().insert(It, sinkMBB);
-      // Update machine-CFG edges
-      BB->addSuccessor(copy0MBB);
-      BB->addSuccessor(sinkMBB);
+    //  thisMBB:
+    //  ...
+    //   cmpTY cr0, r1, r2
+    //   %TrueValue = li 1
+    //   bCC sinkMBB
+    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+    MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+    BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
+    MachineFunction *F = BB->getParent();
+    F->getBasicBlockList().insert(It, copy0MBB);
+    F->getBasicBlockList().insert(It, sinkMBB);
+    // Update machine-CFG edges
+    BB->addSuccessor(copy0MBB);
+    BB->addSuccessor(sinkMBB);
 
-      //  copy0MBB:
-      //   %FalseValue = li 0
-      //   fallthrough
-      BB = copy0MBB;
-      // Update machine-CFG edges
-      BB->addSuccessor(sinkMBB);
+    //  copy0MBB:
+    //   %FalseValue = li 0
+    //   fallthrough
+    BB = copy0MBB;
+    // Update machine-CFG edges
+    BB->addSuccessor(sinkMBB);
 
-      //  sinkMBB:
-      //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
-      //  ...
-      BB = sinkMBB;
-      BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
-        .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
-      return Result;
-    }
-    assert(0 && "Is this legal?");
-    return 0;
+    //  sinkMBB:
+    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+    //  ...
+    BB = sinkMBB;
+    BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
+      .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
+    return Result;
+  }
 
   case ISD::SELECT: {
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 336ec29..fa7518d 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1086,7 +1086,7 @@
     return SelectExpr(N);
 }
 
-unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
+unsigned ISel::SelectCC(SDOperand Cond, unsigned& Opc, bool &Inv, unsigned& Idx) {
   unsigned Result, Tmp1, Tmp2;
   bool AlreadySelected = false;
   static const unsigned CompareOpcodes[] =
@@ -1097,23 +1097,24 @@
 
   // If the first operand to the select is a SETCC node, then we can fold it
   // into the branch that selects which value to return.
-  if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
+  if (Cond.getOpcode() == ISD::SETCC) {
+    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
     bool U;
-    Opc = getBCCForSetCC(SetCC->getCondition(), U);
-    Idx = getCRIdxForSetCC(SetCC->getCondition(), Inv);
+    Opc = getBCCForSetCC(CC, U);
+    Idx = getCRIdxForSetCC(CC, Inv);
 
     // Use U to determine whether the SETCC immediate range is signed or not.
-    if (isIntImmediate(SetCC->getOperand(1), Tmp2) &&
+    if (isIntImmediate(Cond.getOperand(1), Tmp2) &&
         ((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
       Tmp2 = Lo16(Tmp2);
       // For comparisons against zero, we can implicity set CR0 if a recording
       // variant (e.g. 'or.' instead of 'or') of the instruction that defines
       // operand zero of the SetCC node is available.
-      if (0 == Tmp2 &&
-          NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode()) &&
-          SetCC->getOperand(0).Val->hasOneUse()) {
+      if (Tmp2 == 0 &&
+          NodeHasRecordingVariant(Cond.getOperand(0).getOpcode()) &&
+          Cond.getOperand(0).Val->hasOneUse()) {
         RecordSuccess = false;
-        Tmp1 = SelectExpr(SetCC->getOperand(0), true);
+        Tmp1 = SelectExpr(Cond.getOperand(0), true);
         if (RecordSuccess) {
           ++Recorded;
           BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
@@ -1123,16 +1124,16 @@
       }
       // If we could not implicitly set CR0, then emit a compare immediate
       // instead.
-      if (!AlreadySelected) Tmp1 = SelectExpr(SetCC->getOperand(0));
+      if (!AlreadySelected) Tmp1 = SelectExpr(Cond.getOperand(0));
       if (U)
         BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
       else
         BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
     } else {
-      bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
+      bool IsInteger = MVT::isInteger(Cond.getOperand(0).getValueType());
       unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
-      Tmp1 = SelectExpr(SetCC->getOperand(0));
-      Tmp2 = SelectExpr(SetCC->getOperand(1));
+      Tmp1 = SelectExpr(Cond.getOperand(0));
+      Tmp2 = SelectExpr(Cond.getOperand(1));
       BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
   } else {
@@ -1140,7 +1141,7 @@
     // treating it as if it were a boolean.
     Opc = PPC::BNE;
     Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
-    Tmp1 = SelectExpr(CC);
+    Tmp1 = SelectExpr(Cond);
     BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
   }
   return Result;
@@ -2057,111 +2058,105 @@
     return 0;
   }
 
-  case ISD::SETCC:
-    if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-      if (ConstantSDNode *CN =
-          dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
-        // We can codegen setcc op, imm very efficiently compared to a brcond.
-        // Check for those cases here.
-        // setcc op, 0
-        if (CN->getValue() == 0) {
-          Tmp1 = SelectExpr(SetCC->getOperand(0));
-          switch (SetCC->getCondition()) {
-          default: SetCC->dump(); assert(0 && "Unhandled SetCC condition"); abort();
-          case ISD::SETEQ:
-            Tmp2 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);
-            BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp2).addImm(27)
-              .addImm(5).addImm(31);
-            break;
-          case ISD::SETNE:
-            Tmp2 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(-1);
-            BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp2).addReg(Tmp1);
-            break;
-          case ISD::SETLT:
-            BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(1)
-              .addImm(31).addImm(31);
-            break;
-          case ISD::SETGT:
-            Tmp2 = MakeReg(MVT::i32);
-            Tmp3 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
-            BuildMI(BB, PPC::ANDC, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
-            BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
-              .addImm(31).addImm(31);
-            break;
-          }
-          return Result;
+  case ISD::SETCC: {
+    ISD::CondCode CC = cast<CondCodeSDNode>(Node->getOperand(2))->get();
+    if (isIntImmediate(Node->getOperand(1), Tmp3)) {
+      // We can codegen setcc op, imm very efficiently compared to a brcond.
+      // Check for those cases here.
+      // setcc op, 0
+      if (Tmp3 == 0) {
+        Tmp1 = SelectExpr(Node->getOperand(0));
+        switch (CC) {
+        default: Node->dump(); assert(0 && "Unhandled SetCC condition"); abort();
+        case ISD::SETEQ:
+          Tmp2 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp2).addImm(27)
+            .addImm(5).addImm(31);
+          break;
+        case ISD::SETNE:
+          Tmp2 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(-1);
+          BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp2).addReg(Tmp1);
+          break;
+        case ISD::SETLT:
+          BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(1)
+            .addImm(31).addImm(31);
+          break;
+        case ISD::SETGT:
+          Tmp2 = MakeReg(MVT::i32);
+          Tmp3 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::ANDC, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
+            .addImm(31).addImm(31);
+          break;
         }
-        // setcc op, -1
-        if (CN->isAllOnesValue()) {
-          Tmp1 = SelectExpr(SetCC->getOperand(0));
-          switch (SetCC->getCondition()) {
-          default: assert(0 && "Unhandled SetCC condition"); abort();
-          case ISD::SETEQ:
-            Tmp2 = MakeReg(MVT::i32);
-            Tmp3 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(1);
-            BuildMI(BB, PPC::LI, 1, Tmp3).addSImm(0);
-            BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp3);
-            break;
-          case ISD::SETNE:
-            Tmp2 = MakeReg(MVT::i32);
-            Tmp3 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::NOR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
-            BuildMI(BB, PPC::ADDIC, 2, Tmp3).addReg(Tmp2).addSImm(-1);
-            BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp3).addReg(Tmp2);
-            break;
-          case ISD::SETLT:
-            Tmp2 = MakeReg(MVT::i32);
-            Tmp3 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::ADDI, 2, Tmp2).addReg(Tmp1).addSImm(1);
-            BuildMI(BB, PPC::AND, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
-            BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
-              .addImm(31).addImm(31);
-            break;
-          case ISD::SETGT:
-            Tmp2 = MakeReg(MVT::i32);
-            BuildMI(BB, PPC::RLWINM, 4, Tmp2).addReg(Tmp1).addImm(1)
-              .addImm(31).addImm(31);
-            BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp2).addImm(1);
-            break;
-          }
-          return Result;
+        return Result;
+      } else if (Tmp3 == ~0U) {        // setcc op, -1
+        Tmp1 = SelectExpr(Node->getOperand(0));
+        switch (CC) {
+        default: assert(0 && "Unhandled SetCC condition"); abort();
+        case ISD::SETEQ:
+          Tmp2 = MakeReg(MVT::i32);
+          Tmp3 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(1);
+          BuildMI(BB, PPC::LI, 1, Tmp3).addSImm(0);
+          BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp3);
+          break;
+        case ISD::SETNE:
+          Tmp2 = MakeReg(MVT::i32);
+          Tmp3 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::NOR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+          BuildMI(BB, PPC::ADDIC, 2, Tmp3).addReg(Tmp2).addSImm(-1);
+          BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp3).addReg(Tmp2);
+          break;
+        case ISD::SETLT:
+          Tmp2 = MakeReg(MVT::i32);
+          Tmp3 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::ADDI, 2, Tmp2).addReg(Tmp1).addSImm(1);
+          BuildMI(BB, PPC::AND, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
+            .addImm(31).addImm(31);
+          break;
+        case ISD::SETGT:
+          Tmp2 = MakeReg(MVT::i32);
+          BuildMI(BB, PPC::RLWINM, 4, Tmp2).addReg(Tmp1).addImm(1)
+            .addImm(31).addImm(31);
+          BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp2).addImm(1);
+          break;
         }
+        return Result;
       }
-
-      bool Inv;
-      unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
-      MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
-      return Result;
     }
-    assert(0 && "Is this legal?");
-    return 0;
 
+    bool Inv;
+    unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
+    MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
+    return Result;
+  }
   case ISD::SELECT: {
-    SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
-    if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
-        !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
+    SDNode *Cond = N.getOperand(0).Val;
+    ISD::CondCode CC;
+    if (Cond->getOpcode() == ISD::SETCC &&
         !MVT::isInteger(N.getOperand(1).getValueType()) &&
-        !MVT::isInteger(N.getOperand(2).getValueType()) &&
-        SetCC->getCondition() != ISD::SETEQ &&
-        SetCC->getCondition() != ISD::SETNE) {
-      MVT::ValueType VT = SetCC->getOperand(0).getValueType();
+        cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETEQ &&
+        cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETNE) {
+      MVT::ValueType VT = Cond->getOperand(0).getValueType();
+      ISD::CondCode CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
       unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
       unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
 
-      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
+      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Cond->getOperand(1));
       if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
-        switch(SetCC->getCondition()) {
+        switch(CC) {
         default: assert(0 && "Invalid FSEL condition"); abort();
         case ISD::SETULT:
         case ISD::SETLT:
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETUGE:
         case ISD::SETGE:
-          Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+          Tmp1 = SelectExpr(Cond->getOperand(0));   // Val to compare against
           BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
           return Result;
         case ISD::SETUGT:
@@ -2169,11 +2164,11 @@
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETULE:
         case ISD::SETLE: {
-          if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
-            Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
+          if (Cond->getOperand(0).getOpcode() == ISD::FNEG) {
+            Tmp2 = SelectExpr(Cond->getOperand(0).getOperand(0));
           } else {
             Tmp2 = MakeReg(VT);
-            Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+            Tmp1 = SelectExpr(Cond->getOperand(0));   // Val to compare against
             BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
           }
           BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
@@ -2182,10 +2177,10 @@
         }
       } else {
         Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
-        Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
-        Tmp2 = SelectExpr(SetCC->getOperand(1));
+        Tmp1 = SelectExpr(Cond->getOperand(0));   // Val to compare against
+        Tmp2 = SelectExpr(Cond->getOperand(1));
         Tmp3 =  MakeReg(VT);
-        switch(SetCC->getCondition()) {
+        switch(CC) {
         default: assert(0 && "Invalid FSEL condition"); abort();
         case ISD::SETULT:
         case ISD::SETLT:
@@ -2210,7 +2205,6 @@
         }
       }
       assert(0 && "Should never get here");
-      return 0;
     }
 
     bool Inv;
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index dd9918e..36d34ce 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -1663,15 +1663,15 @@
         return false;
       }
 
-  SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Cond);
-  if (SetCC == 0)
+  if (Cond.getOpcode() != ISD::SETCC)
     return true;                       // Can only handle simple setcc's so far.
+  ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
 
   unsigned Opc;
 
   // Handle integer conditions first.
-  if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
-    switch (SetCC->getCondition()) {
+  if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
+    switch (CC) {
     default: assert(0 && "Illegal integer SetCC!");
     case ISD::SETEQ: Opc = X86::JE; break;
     case ISD::SETGT: Opc = X86::JG; break;
@@ -1685,7 +1685,7 @@
     case ISD::SETUGE: Opc = X86::JAE; break;
     }
     Select(Chain);
-    EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
+    EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
     BuildMI(BB, Opc, 1).addMBB(Dest);
     return false;
   }
@@ -1699,7 +1699,7 @@
   //  1 | 0 | 0 | X == Y
   //  1 | 1 | 1 | unordered
   //
-  switch (SetCC->getCondition()) {
+  switch (CC) {
   default: assert(0 && "Invalid FP setcc!");
   case ISD::SETUEQ:
   case ISD::SETEQ:   Opc = X86::JE;  break;     // True if ZF = 1
@@ -1742,7 +1742,7 @@
   }
 
   Select(Chain);
-  EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
+  EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
   BuildMI(BB, Opc, 1).addMBB(Dest);
   if (Opc2)
     BuildMI(BB, Opc2, 1).addMBB(Dest);
@@ -1781,10 +1781,10 @@
     /*CMPNLE*/  6, /*CMPNLT*/   5, /*CMPUNORD*/ 3, /*CMPORD*/   7
   };
   
-  SetCCSDNode *SetCC;
-  if ((SetCC = dyn_cast<SetCCSDNode>(Cond))) {
-    if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
-      switch (SetCC->getCondition()) {
+  if (Cond.getOpcode() == ISD::SETCC) {
+    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
+    if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
+      switch (CC) {
       default: assert(0 && "Unknown integer comparison!");
       case ISD::SETEQ:  CondCode = EQ; break;
       case ISD::SETGT:  CondCode = GT; break;
@@ -1805,7 +1805,7 @@
       //  1 | 0 | 0 | X == Y
       //  1 | 1 | 1 | unordered
       //
-      switch (SetCC->getCondition()) {
+      switch (CC) {
       default: assert(0 && "Unknown FP comparison!");
       case ISD::SETUEQ:
       case ISD::SETEQ:  CondCode = EQ; break;     // True if ZF = 1
@@ -1831,49 +1831,50 @@
         break;
       }
     }
-  }
+  
 
-  // There's no SSE equivalent of FCMOVE.  For cases where we set a condition
-  // code above and one of the results of the select is +0.0, then we can fake 
-  // it up through a clever AND with mask.  Otherwise, we will fall through to
-  // the code below that will use a PHI node to select the right value.
-  if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
-    if (SetCC && SetCC->getOperand(0).getValueType() == SVT && 
-        NOT_SET != CondCode) {
-      ConstantFPSDNode *CT = dyn_cast<ConstantFPSDNode>(True);
-      ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(False);
-      bool TrueZero = CT && CT->isExactlyValue(0.0);
-      bool FalseZero = CF && CF->isExactlyValue(0.0);
-      if (TrueZero || FalseZero) {
-        SDOperand LHS = Cond.getOperand(0);
-        SDOperand RHS = Cond.getOperand(1);
-        
-        // Select the two halves of the condition
-        unsigned RLHS, RRHS;
-        if (getRegPressure(LHS) > getRegPressure(RHS)) {
-          RLHS = SelectExpr(LHS);
-          RRHS = SelectExpr(RHS);
-        } else {
-          RRHS = SelectExpr(RHS);
-          RLHS = SelectExpr(LHS);
+    // There's no SSE equivalent of FCMOVE.  For cases where we set a condition
+    // code above and one of the results of the select is +0.0, then we can fake
+    // it up through a clever AND with mask.  Otherwise, we will fall through to
+    // the code below that will use a PHI node to select the right value.
+    if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
+      if (Cond.getOperand(0).getValueType() == SVT && 
+          NOT_SET != CondCode) {
+        ConstantFPSDNode *CT = dyn_cast<ConstantFPSDNode>(True);
+        ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(False);
+        bool TrueZero = CT && CT->isExactlyValue(0.0);
+        bool FalseZero = CF && CF->isExactlyValue(0.0);
+        if (TrueZero || FalseZero) {
+          SDOperand LHS = Cond.getOperand(0);
+          SDOperand RHS = Cond.getOperand(1);
+          
+          // Select the two halves of the condition
+          unsigned RLHS, RRHS;
+          if (getRegPressure(LHS) > getRegPressure(RHS)) {
+            RLHS = SelectExpr(LHS);
+            RRHS = SelectExpr(RHS);
+          } else {
+            RRHS = SelectExpr(RHS);
+            RLHS = SelectExpr(LHS);
+          }
+          
+          // Emit the comparison and generate a mask from it
+          unsigned MaskReg = MakeReg(SVT);
+          unsigned Opc = (SVT == MVT::f32) ? X86::CMPSSrr : X86::CMPSDrr;
+          BuildMI(BB, Opc, 3, MaskReg).addReg(RLHS).addReg(RRHS)
+            .addImm(SSE_CMOVTAB[CondCode]);
+          
+          if (TrueZero) {
+            RFalse = SelectExpr(False);
+            Opc = (SVT == MVT::f32) ? X86::ANDNPSrr : X86::ANDNPDrr;
+            BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RFalse);
+          } else {
+            RTrue = SelectExpr(True);
+            Opc = (SVT == MVT::f32) ? X86::ANDPSrr : X86::ANDPDrr;
+            BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RTrue);
+          }
+          return;
         }
-        
-        // Emit the comparison and generate a mask from it
-        unsigned MaskReg = MakeReg(SVT);
-        unsigned Opc = (SVT == MVT::f32) ? X86::CMPSSrr : X86::CMPSDrr;
-        BuildMI(BB, Opc, 3, MaskReg).addReg(RLHS).addReg(RRHS)
-          .addImm(SSE_CMOVTAB[CondCode]);
-        
-        if (TrueZero) {
-          RFalse = SelectExpr(False);
-          Opc = (SVT == MVT::f32) ? X86::ANDNPSrr : X86::ANDNPDrr;
-          BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RFalse);
-        } else {
-          RTrue = SelectExpr(True);
-          Opc = (SVT == MVT::f32) ? X86::ANDPSrr : X86::ANDPDrr;
-          BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RTrue);
-        }
-        return;
       }
     }
   }
@@ -3281,7 +3282,7 @@
 
   case ISD::SETCC:
     EmitCMP(N.getOperand(0), N.getOperand(1), Node->hasOneUse());
-    EmitSetCC(BB, Result, cast<SetCCSDNode>(N)->getCondition(),
+    EmitSetCC(BB, Result, cast<CondCodeSDNode>(N.getOperand(2))->get(),
               MVT::isFloatingPoint(N.getOperand(1).getValueType()));
     return Result;
   case ISD::LOAD: