commit 8aa8a5ed27e9146cb3e601a9cdf0ed481893116d
author Chris Lattner <sabre@nondot.org> Sat Jan 26 01:05:42 2008 +0000
committer Chris Lattner <sabre@nondot.org> Sat Jan 26 01:05:42 2008 +0000
tree 225859b61eb744bc0364a59111bfb3d5c8b92981
parent 9ac40e6b8495fec8a9531d5062bcc43162549ff3

don't bother making x&-1 only to simplify it in dag combine.  This commonly occurs expanding i64 ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46383 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index efbaa5a..ad6cd1b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1877,6 +1877,8 @@
     // worth handling here.
     if (N2C && N2C->getValue() == 0)
       return N2;
+    if (N2C && N2C->isAllOnesValue())  // X & -1 -> X
+      return N1;
     break;
   case ISD::OR:
   case ISD::XOR: