Adjust to changes in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index e76bc3b..f06567b 100644
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -8,45 +8,13 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = powerpc
-include $(LEVEL)/Makefile.common
-
TARGET = PowerPC
+
# Make sure that tblgen is run, first thing.
-$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
- PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
+BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
+ PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
-TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
-
-%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) register names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` register information header with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` register information implementation with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) instruction names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` instruction information with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` code emitter with tblgen"
- $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
-
-$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td assembly writer with tblgen"
- $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
-
-clean::
- $(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 3adce5d..44d307d 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -2144,7 +2144,7 @@
if (CI_1 && OrI && OrI->getOpcode() == Instruction::Or) {
Value *Op0 = OrI->getOperand(0);
Value *Op1 = OrI->getOperand(1);
- BinaryOperator *AndI_2;
+ BinaryOperator *AndI_2 = 0;
// Whichever operand our initial And instruction is to the Or instruction,
// Look at the other operand to determine if it is also an And instruction
if (AndI == Op0) {
diff --git a/lib/Target/Skeleton/Makefile b/lib/Target/Skeleton/Makefile
index 725dcba..bc9a16d 100644
--- a/lib/Target/Skeleton/Makefile
+++ b/lib/Target/Skeleton/Makefile
@@ -9,37 +9,11 @@
LEVEL = ../../..
LIBRARYNAME = skeleton
-include $(LEVEL)/Makefile.common
TARGET = Skeleton
-TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
- $(SourceDir)/../Target.td
-
-
# Make sure that tblgen is run, first thing.
-$(SourceDepend): $(TARGET)GenRegisterInfo.h.inc $(TARGET)GenRegisterNames.inc \
- $(TARGET)GenRegisterInfo.inc $(TARGET)GenInstrNames.inc \
- $(TARGET)GenInstrInfo.inc
+BUILT_SOURCES = $(TARGET)GenRegisterInfo.h.inc $(TARGET)GenRegisterNames.inc \
+ $(TARGET)GenRegisterInfo.inc $(TARGET)GenInstrNames.inc \
+ $(TARGET)GenInstrInfo.inc
-$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register information header with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register information implementation with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td instruction names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td instruction information with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-clean::
- $(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common
diff --git a/lib/Target/SparcV9/Makefile b/lib/Target/SparcV9/Makefile
index 4226ddc..788a88a 100644
--- a/lib/Target/SparcV9/Makefile
+++ b/lib/Target/SparcV9/Makefile
@@ -10,48 +10,27 @@
LIBRARYNAME = sparcv9
PARALLEL_DIRS = InstrSched LiveVar ModuloScheduling RegAlloc
-ExtraSource = SparcV9.burm.cpp
+BUILT_SOURCES = \
+ SparcV9CodeEmitter.inc \
+ SparcV9.burm.cpp
include $(LEVEL)/Makefile.common
-ifdef ENABLE_OPTIMIZED
- DEBUG_FLAG =
-else
- DEBUG_FLAG = -D_DEBUG
-endif
+SparcV9.burg.in1 : $(BUILD_SRC_DIR)/SparcV9.burg.in
+ $(CXX) -E $(CPPFLAGS) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
-SparcV9.burg.in1 : $(SourceDir)/SparcV9.burg.in
- $(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
-
-SparcV9.burm : SparcV9.burg.in1 $(LLVM_SRC_ROOT)/include/llvm/Instruction.def
- $(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
+SparcV9.burm : SparcV9.burg.in1
+ $(CXX) -E $(CPPFLAGS) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
SparcV9.burm.cpp: SparcV9.burm
@echo "Burging `basename $<`"
- $(RunBurg) $< -o $@
+ $(BURG) -I $< -o $@
-$(BUILD_OBJ_DIR)/Debug/SparcV9.burm.lo: SparcV9.burm.cpp
- $(CompileG) $< -o $@
+TABLEGEN_FILES := $(notdir $(wildcard $(BUILD_SRC_DIR)/*.td))
-$(BUILD_OBJ_DIR)/Release/SparcV9.burm.lo: SparcV9.burm.cpp
- $(CompileO) $< -o $@
-
-$(BUILD_OBJ_DIR)/Profile/SparcV9.burm.lo: SparcV9.burm.cpp
- $(CompileP) $< -o $@
-
-$(BUILD_OBJ_DIR)/Depend/SparcV9.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
- touch $@
-
-TABLEGEN_FILES := $(notdir $(wildcard $(SourceDir)/*.td))
-
-# Make sure that tblgen is run, first thing.
-$(SourceDepend): SparcV9CodeEmitter.inc
-
-SparcV9CodeEmitter.cpp:: SparcV9CodeEmitter.inc
-
-SparcV9CodeEmitter.inc:: $(SourceDir)/SparcV9.td $(TABLEGEN_FILES) $(TBLGEN)
- @echo "Tblgen'ing `basename $<`"
- $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
+SparcV9CodeEmitter.inc: $(BUILD_SRC_DIR)/SparcV9.td $(TABLEGEN_FILES) $(TBLGEN)
+ @echo "Running tblgen on SparcV9.td"
+ $(TableGen) -gen-emitter -o $@ $<
clean::
$(VERB) $(RM) -f SparcV9CodeEmitter.inc SparcV9.burg.in1 SparcV9.burm SparcV9.burm.cpp
diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index dd74540..bdaf28c 100644
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -8,50 +8,12 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = x86
+TARGET = X86
+# Make sure that tblgen is run, first thing.
+BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
+ X86GenRegisterInfo.inc X86GenInstrNames.inc \
+ X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
+ X86GenIntelAsmWriter.inc
+
include $(LEVEL)/Makefile.common
-TARGET = X86
-
-# Make sure that tblgen is run, first thing.
-$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
- X86GenRegisterInfo.inc X86GenInstrNames.inc \
- X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
- X86GenIntelAsmWriter.inc
-
-TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
- $(SourceDir)/../Target.td
-
-$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register information header with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td register info implementation with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td instruction names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td instruction information with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td AT&T assembly writer with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
-
-$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td Intel assembly writer with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
-
-#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
-# @echo "Building $(TARGET).td instruction selector with tblgen"
-# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
-
-clean::
- $(VERB) rm -f *.inc