commit 8c65f6e71c1d46d823b9a884819992a9255edd54
author Benjamin Kramer <benny.kra@googlemail.com> Tue Jan 05 21:05:54 2010 +0000
committer Benjamin Kramer <benny.kra@googlemail.com> Tue Jan 05 21:05:54 2010 +0000
tree 8fbef7d34f7ad7c92c4448013b6f60282eb53d14
parent 718bf3f89d69f76791fec73b1edd55c450a93f12

Move remaining stuff to the isInteger predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92771 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1fdb494..0367165 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -7535,8 +7535,7 @@
 
 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
   // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
-  return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
-         Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
+  return Ty1->isInteger(64) && Ty2->isInteger(64) && Subtarget->is64Bit();
 }
 
 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {