CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
Discovered interesting DAGCombiner feature, which is currently solved via
custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
insists on inserting one anyway.)
- Update README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 5802eb6..91d52fa 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -134,6 +134,7 @@
case SPU::ORi64_v2i64:
case SPU::ORf32_v4f32:
case SPU::ORf64_v2f64:
+/*
case SPU::ORi128_r64:
case SPU::ORi128_f64:
case SPU::ORi128_r32:
@@ -148,6 +149,8 @@
case SPU::ORr16_i128:
case SPU::ORr8_i128:
case SPU::ORvec_i128:
+*/
+/*
case SPU::ORr16_r32:
case SPU::ORr8_r32:
case SPU::ORr32_r16:
@@ -158,7 +161,11 @@
case SPU::ORr64_r32:
case SPU::ORr64_r16:
case SPU::ORr64_r8:
- {
+*/
+ case SPU::ORf32_r32:
+ case SPU::ORr32_f32:
+ case SPU::ORf64_r64:
+ case SPU::ORr64_f64: {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&