commit 8c90d2a37fdd3b14401035810d3644b2591b992a
author Anton Korobeynikov <asl@math.spbu.ru> Wed Feb 20 11:22:39 2008 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Wed Feb 20 11:22:39 2008 +0000
tree 650146d45463c89eddd4e9be73a224d638b880dd
parent 53422f6643586cded61578fdd22bc3a94b5f9c91

Remove bunch of gcc 4.3-related warnings from Target


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMCodeEmitter.cpp

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 62ea102..f4ee6b0 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -475,8 +475,8 @@
         }
       }
       // set the field related to shift operations (except rrx).
-      if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
-        if(IsShiftByRegister) {
+      if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
+        if (IsShiftByRegister) {
           // set the value of bit[11:8] (register Rs).
           assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
           op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
@@ -487,6 +487,7 @@
           op = ARM_AM::getSORegOffset(MO2.getImm());
           Value |= op << 7;
         }
+      }
       break;
     }
     default: assert(false && "Unknown operand type!");