commit 8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde
author Chris Lattner <sabre@nondot.org> Mon Jan 07 02:39:19 2008 +0000
committer Chris Lattner <sabre@nondot.org> Mon Jan 07 02:39:19 2008 +0000
tree b9e21ae796516ae90af9ada2915fadf2cf616e53
parent 572742e876478d3ec7ff0750c0473d7621804b15

Add predicates methods to TargetOperandInfo, and switch all clients 
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 40ab4c2..49b7ef2 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -541,7 +541,7 @@
   const TargetInstrDescriptor *TID = getDesc();
   if (TID->isPredicable()) {
     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+      if (TID->OpInfo[i].isPredicate())
         return i;
   }
 
@@ -591,7 +591,7 @@
   const TargetInstrDescriptor *TID = MI->getDesc();
   if (TID->isPredicable()) {
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+      if (TID->OpInfo[i].isPredicate()) {
         // Predicated operands must be last operands.
         addOperand(MI->getOperand(i));
       }

lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3ef907e..e3e54c5 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -296,9 +296,9 @@
     assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
     return NULL;
   }
-  const TargetOperandInfo &toi = II->OpInfo[Op];
-  return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
-         ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+  if (II->OpInfo[Op].isLookupPtrRegClass())
+    return TII->getPointerRegClass();
+  return MRI->getRegClass(II->OpInfo[Op].RegClass);
 }
 
 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
@@ -435,7 +435,7 @@
     unsigned VReg = getVR(Op, VRBaseMap);
     const TargetInstrDescriptor *TID = MI->getDesc();
     bool isOptDef = (IIOpNum < TID->numOperands)
-      ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+      ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
     MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
     
     // Verify that it is right.

lib/CodeGen/TargetInstrInfoImpl.cpp

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 207f371..4498c98 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -38,7 +38,7 @@
   const TargetInstrDescriptor *TID = MI->getDesc();
   if (TID->isPredicable()) {
     for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+      if (TID->OpInfo[i].isPredicate()) {
         MachineOperand &MO = MI->getOperand(i);
         if (MO.isReg()) {
           MO.setReg(Pred[j].getReg());