Tidy up spacing. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167671 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index af1c3b6..fc1ca5c 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -12840,8 +12840,8 @@
// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
// or XMM0_V32I8 in AVX all of this code can be replaced with that
// in the .td file.
-static MachineBasicBlock * EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
- const TargetInstrInfo *TII) {
+static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
+ const TargetInstrInfo *TII) {
unsigned Opc;
switch (MI->getOpcode()) {
default: llvm_unreachable("illegal opcode!");
@@ -12877,8 +12877,8 @@
// FIXME: Custom handling because TableGen doesn't support multiple implicit
// defs in an instruction pattern
-static MachineBasicBlock * EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
- const TargetInstrInfo *TII) {
+static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
+ const TargetInstrInfo *TII) {
unsigned Opc;
switch (MI->getOpcode()) {
default: llvm_unreachable("illegal opcode!");