commit 8d1837d9bebdc36fb67e0291cb23bc6bce43d44d
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:56:42 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:56:42 2009 +0000
tree 1c2c17bde45eb203d3da8a7dcbc385ece98c5722
parent 11275eba1747f82276a8f954c13f3ff4881e995b

Provide "wide" muls and divs/rems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 9734709..0348e1e 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -83,18 +83,20 @@
     CommonRC = 0;
 
   if (CommonRC) {
-    unsigned Opc;
     if (CommonRC == &SystemZ::GR64RegClass ||
         CommonRC == &SystemZ::ADDR64RegClass) {
-      Opc = SystemZ::MOV64rr;
+      BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
     } else if (CommonRC == &SystemZ::GR32RegClass ||
                CommonRC == &SystemZ::ADDR32RegClass) {
-      Opc = SystemZ::MOV32rr;
+      BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
+    } else if (CommonRC == &SystemZ::GR64PRegClass) {
+      BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
+    } else if (CommonRC == &SystemZ::GR128RegClass) {
+      BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
     } else {
       return false;
     }
 
-    BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
     return true;
   }
 
@@ -126,6 +128,8 @@
     return false;
   case SystemZ::MOV32rr:
   case SystemZ::MOV64rr:
+  case SystemZ::MOV64rrP:
+  case SystemZ::MOV128rr:
     assert(MI.getNumOperands() >= 2 &&
            MI.getOperand(0).isReg() &&
            MI.getOperand(1).isReg() &&