commit 8e0c7697fd9b9354856074efc06eea9f6d80015c
author Jim Grosbach <grosbach@apple.com> Fri Sep 02 18:46:15 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Fri Sep 02 18:46:15 2011 +0000
tree 1a493066c47653a0672282f9b6fa58a239ac706e
parent 9dc31e87051715f2db5012794e9089ac0f7f30d3

Tidy up. Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 89918f9..7872cb9 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -869,7 +869,7 @@
     case ARM::RRX: {
       // This encodes as "MOVs Rd, Rm, rrx
       MachineInstrBuilder MIB =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
                                MI.getOperand(0).getReg())
                        .addOperand(MI.getOperand(1))
                        .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))