Floating point loads/stores act on memory operands. Rename them to
denote this fact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11971 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 3406185..63a9abe 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -772,7 +772,7 @@
// is misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction.
- if (MI->getOpcode() == X86::FSTPr80) {
+ if (MI->getOpcode() == X86::FSTPm80) {
if ((MI->getOperand(0).getReg() == X86::ESP)
&& (MI->getOperand(1).getImmedValue() == 1)) {
if (Op3.isImmediate() &&
@@ -793,7 +793,7 @@
// misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fld DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction.
- if (MI->getOpcode() == X86::FLDr80 &&
+ if (MI->getOpcode() == X86::FLDm80 &&
MI->getOperand(0).getReg() == X86::ESP &&
MI->getOperand(1).getImmedValue() == 1) {
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
@@ -813,7 +813,7 @@
// 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
// [...]", which is wrong. Workaround: Output the raw opcode bytes
// instead of the instruction.
- if (MI->getOpcode() == X86::FILDr64 &&
+ if (MI->getOpcode() == X86::FILDm64 &&
MI->getOperand(0).getReg() == X86::ESP &&
MI->getOperand(1).getImmedValue() == 1) {
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
@@ -834,7 +834,7 @@
// "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
// "fistpll DWORD PTR " instead, which is what libopcodes is
// expecting to see.
- if (MI->getOpcode() == X86::FISTPr64) {
+ if (MI->getOpcode() == X86::FISTPm64) {
O << "fistpll DWORD PTR ";
printMemReference(MI, 0);
if (MI->getNumOperands() == 5) {