commit 8e59ea998f1357768aa43cb00187e6c1c1a1cc7e
author Evan Cheng <evan.cheng@apple.com> Wed Feb 07 00:06:56 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Feb 07 00:06:56 2007 +0000
tree 9faddd5219816cb2829887a41040b7d1a7ad5f5d
parent c67da0cf13e2d671061449e8da4ffe102e5fc848

Spill / restore should avoid modifying the condition register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 6adf645..36ed76d 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -83,7 +83,7 @@
       return MI->getOperand(0).getReg();
     }
     break;
-  case ARM::tLDRspi:
+  case ARM::tRestore:
     if (MI->getOperand(1).isFrameIndex() &&
         MI->getOperand(2).isImmediate() && 
         MI->getOperand(2).getImmedValue() == 0) {
@@ -117,7 +117,7 @@
       return MI->getOperand(0).getReg();
     }
     break;
-  case ARM::tSTRspi:
+  case ARM::tSpill:
     if (MI->getOperand(1).isFrameIndex() &&
         MI->getOperand(2).isImmediate() && 
         MI->getOperand(2).getImmedValue() == 0) {