commit 8e5f2c6f65841542e2a7092553fe42a00048e4c7
author Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
committer Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
tree 24fe54b796f3f450ba6aff12b7357068ca66e341
parent 0e5f1306b059b62d7725f324e087efbc8e7a782d

Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrInfo.cpp

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index cc29bae..403adec 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -190,7 +190,7 @@
   else 
     assert(0 && "Can't store this register");
 
-  MachineInstrBuilder MIB = BuildMI(get(Opc))
+  MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
     .addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
@@ -241,7 +241,7 @@
   else 
     assert(0 && "Can't load this register");
 
-  MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isRegister())
@@ -273,12 +273,12 @@
       if (Ops[0] == 0) {    // COPY -> STORE
         unsigned SrcReg = MI->getOperand(2).getReg();
         bool isKill = MI->getOperand(2).isKill();
-        NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
+        NewMI = BuildMI(MF, get(Mips::SW)).addFrameIndex(FI)
           .addImm(0).addReg(SrcReg, false, false, isKill);
       } else {              // COPY -> LOAD
         unsigned DstReg = MI->getOperand(0).getReg();
         bool isDead = MI->getOperand(0).isDead();
-        NewMI = BuildMI(get(Mips::LW))
+        NewMI = BuildMI(MF, get(Mips::LW))
           .addReg(DstReg, true, false, false, isDead)
           .addImm(0).addFrameIndex(FI);
       }
@@ -304,12 +304,12 @@
       if (Ops[0] == 0) {    // COPY -> STORE
         unsigned SrcReg = MI->getOperand(1).getReg();
         bool isKill = MI->getOperand(1).isKill();
-        NewMI = BuildMI(get(StoreOpc)).addFrameIndex(FI)
+        NewMI = BuildMI(MF, get(StoreOpc)).addFrameIndex(FI)
           .addImm(0).addReg(SrcReg, false, false, isKill);
       } else {              // COPY -> LOAD
         unsigned DstReg = MI->getOperand(0).getReg();
         bool isDead = MI->getOperand(0).isDead();
-        NewMI = BuildMI(get(LoadOpc))
+        NewMI = BuildMI(MF, get(LoadOpc))
           .addReg(DstReg, true, false, false, isDead)
           .addImm(0).addFrameIndex(FI);
       }