commit 8e63dcebcc3256a9bf656c21f163b478b82e00a6
author Misha Brukman <brukman+llvm@gmail.com> Thu Aug 12 02:51:38 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Thu Aug 12 02:51:38 2004 +0000
tree 909bb6a2c1439201bfc19d1ebe984fff60fbc0a4
parent a5de823844dc2194ea2fc69359ded9848d6cb6e5

Eliminate special-casing 14-bit immediate load/store opcodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15677 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC64AsmPrinter.cpp

diff --git a/lib/Target/PowerPC/PPC64AsmPrinter.cpp b/lib/Target/PowerPC/PPC64AsmPrinter.cpp
index 11904c1..02f316c 100644
--- a/lib/Target/PowerPC/PPC64AsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPC64AsmPrinter.cpp
@@ -570,8 +570,11 @@
   }
 
   O << TII.getName(Opcode) << " ";
-  if (Opcode == PPC::LD || Opcode == PPC::LWA || 
-      Opcode == PPC::STDU || Opcode == PPC::STDUX) {
+  if (Opcode == PPC::BLR || Opcode == PPC::NOP) {
+    // FIXME: BuildMI() should handle 0 params
+    O << "\n";
+  } else if (ArgCount == 3 && 
+             (ArgType[1] == PPCII::Disimm16 || ArgType[1] == PPCII::Disimm14)) {
     printOp(MI->getOperand(0));
     O << ", ";
     MachineOperand MO = MI->getOperand(1);
@@ -582,20 +585,6 @@
     O << "(";
     printOp(MI->getOperand(2));
     O << ")\n";
-  } else if (Opcode == PPC::BLR || Opcode == PPC::NOP) {
-    // FIXME: BuildMI() should handle 0 params
-    O << "\n";
-  } else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
-    printOp(MI->getOperand(0));
-    O << ", ";
-    printImmOp(MI->getOperand(1), ArgType[1]);
-    O << "(";
-    if (MI->getOperand(2).hasAllocatedReg() &&
-        MI->getOperand(2).getReg() == PPC::R0)
-      O << "0";
-    else
-      printOp(MI->getOperand(2));
-    O << ")\n";
   } else {
     for (i = 0; i < ArgCount; ++i) {
       // addi and friends