commit 8e93de1fd77ffc86d156312878c289a9b779d156
author Sanjiv Gupta <sanjiv.gupta@microchip.com> Thu Jun 25 11:03:14 2009 +0000
committer Sanjiv Gupta <sanjiv.gupta@microchip.com> Thu Jun 25 11:03:14 2009 +0000
tree 0cf2c9299de8651dfef66cf7d2e573992b86d4a8
parent 179f3a329b3dad9954a8cf10f5339cb9fdf7bf89

Identify unconditional gotos and generate a page sel instructions before them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74172 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PIC16/PIC16MemSelOpt.cpp

diff --git a/lib/Target/PIC16/PIC16MemSelOpt.cpp b/lib/Target/PIC16/PIC16MemSelOpt.cpp
index 20f926d..43d47ae 100644
--- a/lib/Target/PIC16/PIC16MemSelOpt.cpp
+++ b/lib/Target/PIC16/PIC16MemSelOpt.cpp
@@ -109,7 +109,7 @@
 
   // If this insn is not going to access any memory, return.
   const TargetInstrDesc &TID = TII->get(MI->getOpcode());
-  if (! (TID.isCall() || TID.mayLoad() || TID.mayStore()))
+  if (!(TID.isBranch() || TID.isCall() || TID.mayLoad() || TID.mayStore()))
     return false;
 
   // Scan for the memory address operand.
@@ -119,8 +119,9 @@
   for (unsigned i = 0; i < NumOperands; i++) {
     MachineOperand Op = MI->getOperand(i);
     if (Op.getType() ==  MachineOperand::MO_GlobalAddress ||
-        Op.getType() ==  MachineOperand::MO_ExternalSymbol) {
-      // We found one mem operand. Next one should be BS.
+        Op.getType() ==  MachineOperand::MO_ExternalSymbol || 
+        Op.getType() ==  MachineOperand::MO_MachineBasicBlock) {
+      // We found one mem operand. Next one may be BS.
       MemOpPos = i;
       break;
     }
@@ -133,7 +134,8 @@
   MachineOperand &Op = MI->getOperand(MemOpPos);
 
   // If this is a pagesel material, handle it first.
-  if (MI->getOpcode() == PIC16::CALL) {
+  if (MI->getOpcode() == PIC16::CALL ||
+      MI->getOpcode() == PIC16::br_uncond) {
     DebugLoc dl = MI->getDebugLoc();
     BuildMI(*MBB, MI, dl, TII->get(PIC16::pagesel)).
       addOperand(Op);