Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 1b321b6..0e5c505 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -180,3 +180,40 @@
}
return 0;
}
+
+void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const
+{
+ if (DestRC != SrcRC) {
+ cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+ abort();
+ }
+
+ if (DestRC == SPU::R8CRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
+ } else if (DestRC == SPU::R16CRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
+ } else if (DestRC == SPU::R32CRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
+ } else if (DestRC == SPU::R32FPRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
+ } else if (DestRC == SPU::R64CRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
+ } else if (DestRC == SPU::R64FPRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
+ } else if (DestRC == SPU::GPRCRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
+ } else if (DestRC == SPU::VECREGRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
+ } else {
+ std::cerr << "Attempt to copy unknown/unsupported register class!\n";
+ abort();
+ }
+}