commit 8f40f7b8676ae7931baaecb1046a21f09471384b
author Elena Demikhovsky <elena.demikhovsky@intel.com> Sun Jul 01 06:12:26 2012 +0000
committer Elena Demikhovsky <elena.demikhovsky@intel.com> Sun Jul 01 06:12:26 2012 +0000
tree 7e9c81e2818a4f270446083b06f705e087618b1d
parent 51e89c0d6ab7ec7d6c816c845447b1c3267775a3

Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e6a0df7..ba66593 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5047,8 +5047,16 @@
 
       SDValue Sc = Op.getOperand(0);
       if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
-          Sc.getOpcode() != ISD::BUILD_VECTOR)
-        return SDValue();
+          Sc.getOpcode() != ISD::BUILD_VECTOR) {
+
+        if (!Subtarget->hasAVX2())
+          return SDValue();
+
+        // Use the register form of the broadcast instruction available on AVX2.
+        if (VT.is256BitVector())
+          Sc = Extract128BitVector(Sc, 0, DAG, dl);
+        return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
+      }
 
       Ld = Sc.getOperand(0);
       ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||