Add testcase for RRX and ASRS (which effectively tests MOVs, since those
are just forms of that instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116538 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll
index a165160..00522da 100644
--- a/test/MC/ARM/simple-encoding.ll
+++ b/test/MC/ARM/simple-encoding.ll
@@ -90,5 +90,13 @@
ret i32 42405
}
+define i64 @f10(i64 %a) nounwind readnone ssp {
+entry:
+; CHECK: f10
+; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
+; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
+ %shr = ashr i64 %a, 1
+ ret i64 %shr
+}
declare void @llvm.trap() nounwind