Implement very primitive hinting support in RegAllocGreedy.
The hint is simply tried first and then forgotten if it couldn't be allocated
immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121306 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 5f2be81..c88d474 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -70,7 +70,7 @@
virtual Spiller &spiller() { return *SpillerInstance; }
- virtual float getPriority(LiveInterval *LI) { return LI->weight; }
+ virtual float getPriority(LiveInterval *LI);
virtual unsigned selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs);
@@ -126,6 +126,22 @@
RegAllocBase::releaseMemory();
}
+float RAGreedy::getPriority(LiveInterval *LI) {
+ float Priority = LI->weight;
+
+ // Prioritize hinted registers so they are allocated first.
+ std::pair<unsigned, unsigned> Hint;
+ if (Hint.first || Hint.second) {
+ // The hint can be target specific, a virtual register, or a physreg.
+ Priority *= 2;
+
+ // Prefer physreg hints above anything else.
+ if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
+ Priority *= 2;
+ }
+ return Priority;
+}
+
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
// Populate a list of physical register spill candidates.
@@ -135,6 +151,14 @@
const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
+ // Preferred physical register computed from hints.
+ unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
+
+ // Try a hinted allocation.
+ if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
+ checkPhysRegInterference(VirtReg, Hint) == 0)
+ return Hint;
+
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
E = TRC->allocation_order_end(*MF);
I != E; ++I) {