make CAS work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47799 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 4cb9491..6c7f5fe 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5358,10 +5358,10 @@
case MVT::i32: Reg = X86::EAX; size = 4; break;
};
SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
- Op.getOperand(2), SDOperand());
+ Op.getOperand(3), SDOperand());
SDOperand Ops[] = { cpIn.getValue(0),
Op.getOperand(1),
- Op.getOperand(3),
+ Op.getOperand(2),
DAG.getTargetConstant(size, MVT::i8),
cpIn.getValue(1) };
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a109dc6..134aeb6 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -2548,6 +2548,7 @@
//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
// prefixes should be correct
+
let Defs = [EAX, EFLAGS], Uses = [EAX] in {
def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
"cmpxchgl $swap,$ptr", []>, TB;