Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 9fbae68..4cdf064 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -104,7 +104,8 @@
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
- bool isKill, bool isDead) {
+ bool isKill, bool isDead,
+ bool isEarlyClobber) {
// If this operand is already a register operand, use setReg to update the
// register's use/def lists.
if (isReg()) {
@@ -126,6 +127,7 @@
IsImp = isImp;
IsKill = isKill;
IsDead = isDead;
+ IsEarlyClobber = isEarlyClobber;
SubReg = 0;
}
@@ -181,13 +183,15 @@
OS << "%mreg" << getReg();
}
- if (isDef() || isKill() || isDead() || isImplicit()) {
+ if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
OS << "<";
bool NeedComma = false;
if (isImplicit()) {
OS << (isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (isDef()) {
+ if (isEarlyClobber())
+ OS << "earlyclobber,";
OS << "def";
NeedComma = true;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 52b2cf4..ffe5c5c 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -592,6 +592,13 @@
MI->addOperand(MachineOperand::CreateReg(Reg, true));
}
break;
+ case 6: // Def of earlyclobber register.
+ for (; NumVals; --NumVals, ++i) {
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
+ false, 0, true));
+ }
+ break;
case 1: // Use of register.
case 3: // Immediate.
case 4: // Addressing mode.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index f6a6d7a..51f7a75 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4939,8 +4939,10 @@
// Add information to the INLINEASM node to know that this register is
// set.
- OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
- AsmNodeOperands);
+ OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
+ 6 /* EARLYCLOBBER REGDEF */ :
+ 2 /* REGDEF */ ,
+ DAG, AsmNodeOperands);
break;
}
case InlineAsm::isInput: {
@@ -4959,6 +4961,7 @@
unsigned NumOps =
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
+ (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
(NumOps & 7) == 4 /*MEM*/) &&
"Skipped past definitions?");
CurOp += (NumOps>>3)+1;
@@ -4966,7 +4969,8 @@
unsigned NumOps =
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
- if ((NumOps & 7) == 2 /*REGDEF*/) {
+ if ((NumOps & 7) == 2 /*REGDEF*/
+ || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
// Add NumOps>>3 registers to MatchedRegs.
RegsForValue MatchedRegs;
MatchedRegs.TLI = &TLI;