Add support for the rep movs[bwd] instructions, and emit them when code
generating the llvm.memcpy intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11351 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index be6319cd..83e5e10 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -470,6 +470,9 @@
unsigned Opcode = MI.getOpcode();
const TargetInstrDescriptor &Desc = II->get(Opcode);
+ // Emit the repeat opcode prefix as needed.
+ if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
+
// Emit instruction prefixes if necessary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
@@ -477,6 +480,7 @@
case X86II::TB:
MCE.emitByte(0x0F); // Two-byte opcode prefix
break;
+ case X86II::REP: break; // already handled.
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
MCE.emitByte(0xD8+