Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 98f4b7d..42a61c6 100644
--- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1325,7 +1325,8 @@
false, false, false);
else {
AsmPrinter *AP = const_cast<AsmPrinter*>(this);
- if ((OpFlags & 7) == 4 /*ADDR MODE*/) {
+ if ((OpFlags & 7) == 4 /*ADDR MODE*/ ||
+ (OpFlags & 7) == 7) /*ADDR MODE OVERLAPS EARLYCLOBBER*/ {
Error = AP->PrintAsmMemoryOperand(MI, OpNo, AsmPrinterVariant,
Modifier[0] ? Modifier : 0);
} else {
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 577400c..cb83194 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -673,7 +673,10 @@
/// registers. for some ordering of the machine instructions [1,N] a
/// live interval is an interval [i, j) where 1 <= i <= j < N for
/// which a variable is live
-void LiveIntervals::computeIntervals() {
+void LiveIntervals::computeIntervals() {
+ AsmsThatEarlyClobber.clear();
+ AsmsWithEarlyClobberConflict.clear();
+
DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
<< "********** Function: "
<< ((Value*)mf_->getFunction())->getName() << '\n';
@@ -710,8 +713,17 @@
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
- if (MO.isRegister() && MO.getReg() && MO.isDef())
+ if (MO.isRegister() && MO.getReg() && MO.isDef()) {
handleRegisterDef(MBB, MI, MIIndex, MO, i);
+ if (MO.isEarlyClobber()) {
+ AsmsThatEarlyClobber.insert(std::make_pair(MO.getReg(), MI));
+ }
+ }
+ if (MO.isRegister() && !MO.isDef() &&
+ MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()) &&
+ MO.overlapsEarlyClobber()) {
+ AsmsWithEarlyClobberConflict.insert(std::make_pair(MO.getReg(), MI));
+ }
}
MIIndex += InstrSlots::NUM;
@@ -740,6 +752,72 @@
return ResVal;
}
+/// noEarlyclobberConflict - see whether virtual reg VReg has a conflict with
+/// hard reg HReg because of earlyclobbers.
+///
+/// Earlyclobber operands may not be assigned the same register as
+/// each other, or as earlyclobber-conflict operands (i.e. those that
+/// are non-earlyclobbered inputs to an asm that also has earlyclobbers).
+///
+/// Thus there are two cases to check for:
+/// 1. VReg is an earlyclobber-conflict register and HReg is an earlyclobber
+/// register in some asm that also has VReg as an input.
+/// 2. VReg is an earlyclobber register and HReg is an earlyclobber-conflict
+/// input elsewhere in some asm.
+/// In both cases HReg can be assigned by the user, or assigned early in
+/// register allocation.
+///
+/// Dropping the distinction between earlyclobber and earlyclobber-conflict,
+/// keeping only one multimap, looks promising, but two earlyclobber-conflict
+/// operands may be assigned the same register if they happen to contain the
+/// same value, and that implementation would prevent this.
+///
+bool LiveIntervals::noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm,
+ unsigned HReg) {
+ typedef std::multimap<unsigned, MachineInstr*>::iterator It;
+
+ // Short circuit the most common case.
+ if (AsmsWithEarlyClobberConflict.size()!=0) {
+ std::pair<It, It> x = AsmsWithEarlyClobberConflict.equal_range(VReg);
+ for (It I = x.first; I!=x.second; I++) {
+ MachineInstr* MI = I->second;
+ for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister() && MO.isEarlyClobber()) {
+ unsigned PhysReg = MO.getReg();
+ if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
+ if (!vrm.hasPhys(PhysReg))
+ continue;
+ PhysReg = vrm.getPhys(PhysReg);
+ }
+ if (PhysReg==HReg)
+ return false;
+ }
+ }
+ }
+ }
+ // Short circuit the most common case.
+ if (AsmsThatEarlyClobber.size()!=0) {
+ std::pair<It, It> x = AsmsThatEarlyClobber.equal_range(VReg);
+ for (It I = x.first; I!=x.second; I++) {
+ MachineInstr* MI = I->second;
+ for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister() && MO.overlapsEarlyClobber()) {
+ unsigned PhysReg = MO.getReg();
+ if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
+ if (!vrm.hasPhys(PhysReg))
+ continue;
+ PhysReg = vrm.getPhys(PhysReg);
+ }
+ if (PhysReg==HReg)
+ return false;
+ }
+ }
+ }
+ }
+ return true;
+}
LiveInterval* LiveIntervals::createInterval(unsigned reg) {
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 7f2a7b6..a365f20 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -109,6 +109,7 @@
// register's use/def lists.
if (isRegister()) {
assert(!isEarlyClobber());
+ assert(!isEarlyClobber() && !overlapsEarlyClobber());
setReg(Reg);
} else {
// Otherwise, change this to a register and set the reg#.
@@ -128,6 +129,7 @@
IsKill = isKill;
IsDead = isDead;
IsEarlyClobber = false;
+ OverlapsEarlyClobber = false;
SubReg = 0;
}
@@ -183,13 +185,20 @@
OS << "%mreg" << getReg();
}
- if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
+ if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber() ||
+ overlapsEarlyClobber()) {
OS << "<";
bool NeedComma = false;
+ if (overlapsEarlyClobber()) {
+ NeedComma = true;
+ OS << "overlapsearly";
+ }
if (isImplicit()) {
+ if (NeedComma) OS << ",";
OS << (isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (isDef()) {
+ if (NeedComma) OS << ",";
if (isEarlyClobber())
OS << "earlyclobber,";
OS << "def";
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 2cfa755..a99ccab 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -1050,7 +1050,8 @@
TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
assert(I != E && "No allocatable register in this register class!");
for (; I != E; ++I)
- if (prt_->isRegAvail(*I)) {
+ if (prt_->isRegAvail(*I) &&
+ li_->noEarlyclobberConflict(cur->reg, *vrm_, *I)) {
FreeReg = *I;
if (FreeReg < inactiveCounts.size())
FreeRegInactiveCount = inactiveCounts[FreeReg];
@@ -1070,7 +1071,8 @@
for (; I != E; ++I) {
unsigned Reg = *I;
if (prt_->isRegAvail(Reg) && Reg < inactiveCounts.size() &&
- FreeRegInactiveCount < inactiveCounts[Reg]) {
+ FreeRegInactiveCount < inactiveCounts[Reg] &&
+ li_->noEarlyclobberConflict(cur->reg, *vrm_, Reg)) {
FreeReg = Reg;
FreeRegInactiveCount = inactiveCounts[Reg];
if (FreeRegInactiveCount == MaxInactiveCount)
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 4ea2906..d929aaf 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -231,7 +231,8 @@
void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum,
const TargetInstrDesc *II,
- DenseMap<SDValue, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap,
+ bool overlapsEarlyClobber) {
if (Op.isMachineOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@@ -244,7 +245,9 @@
const TargetInstrDesc &TID = MI->getDesc();
bool isOptDef = IIOpNum < TID.getNumOperands() &&
TID.OpInfo[IIOpNum].isOptionalDef();
- MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
+ MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, false, false,
+ false, 0, false,
+ overlapsEarlyClobber));
// Verify that it is right.
assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -278,7 +281,9 @@
const ConstantFP *CFP = F->getConstantFPValue();
MI->addOperand(MachineOperand::CreateFPImm(CFP));
} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
- MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
+ MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, false,
+ false, false, 0, false,
+ overlapsEarlyClobber));
} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
} else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
@@ -314,7 +319,9 @@
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addOperand(MachineOperand::CreateReg(VReg, false));
+ MI->addOperand(MachineOperand::CreateReg(VReg, false, false,
+ false, false, 0, false,
+ overlapsEarlyClobber));
// Verify that it is right. Note that the reg class of the physreg and the
// vreg don't necessarily need to match, but the target copy insertion has
@@ -596,6 +603,7 @@
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
+ bool overlapsEarlyClobber = false;
unsigned Flags =
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
unsigned NumVals = Flags >> 3;
@@ -618,13 +626,18 @@
false, 0, true));
}
break;
+ case 7: // Addressing mode overlapping earlyclobber.
+ case 5: // Use of register overlapping earlyclobber.
+ overlapsEarlyClobber = true;
+ // fall through
case 1: // Use of register.
case 3: // Immediate.
case 4: // Addressing mode.
// The addressing mode has been selected, just add all of the
// operands to the machine instruction.
for (; NumVals; --NumVals, ++i)
- AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
+ AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
+ overlapsEarlyClobber);
break;
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 62a6b4f..9492b33 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4909,8 +4909,10 @@
assert(OpInfo.isIndirect && "Memory output must be indirect operand");
// Add information to the INLINEASM node to know about this output.
- unsigned ResOpType = 4/*MEM*/ | (1 << 3);
- AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+ unsigned ResOpType = SawEarlyClobber ?
+ 7 /* MEM OVERLAPS EARLYCLOBBER */ :
+ 4/*MEM*/;
+ AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
TLI.getPointerTy()));
AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
@@ -4963,7 +4965,8 @@
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
(NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
- (NumOps & 7) == 4 /*MEM*/) &&
+ (NumOps & 7) == 4 /*MEM*/ ||
+ (NumOps & 7) == 7 /*MEM OVERLAPS EARLYCLOBBER*/) &&
"Skipped past definitions?");
CurOp += (NumOps>>3)+1;
}
@@ -4985,14 +4988,17 @@
// Use the produced MatchedRegs object to
MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
- MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
+ MatchedRegs.AddInlineAsmOperands(SawEarlyClobber ?
+ 1 /*REGUSE*/ :
+ 5 /*REGUSE OVERLAPS EARLYCLOBBER*/,
+ DAG, AsmNodeOperands);
break;
} else {
- assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
+ assert(((NumOps & 7) == 7/*MEM OVERLAPS EARLYCLOBBER */ ||
+ (NumOps & 7) == 4) && "Unknown matching constraint!");
assert((NumOps >> 3) == 1 && "Unexpected number of operands");
// Add information to the INLINEASM node to know about this input.
- unsigned ResOpType = 4/*MEM*/ | (1 << 3);
- AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+ AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
TLI.getPointerTy()));
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
break;
@@ -5024,8 +5030,10 @@
"Memory operands expect pointer values");
// Add information to the INLINEASM node to know about this input.
- unsigned ResOpType = 4/*MEM*/ | (1 << 3);
- AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+ unsigned ResOpType = SawEarlyClobber ?
+ 7 /* MEM OVERLAPS EARLYCLOBBER */ :
+ 4/*MEM*/;
+ AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
TLI.getPointerTy()));
AsmNodeOperands.push_back(InOperandVal);
break;
@@ -5043,16 +5051,18 @@
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
- OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
- AsmNodeOperands);
+ OpInfo.AssignedRegs.AddInlineAsmOperands(SawEarlyClobber ?
+ 5 /*REGUSE OVERLAPS EARLYCLOBBER*/:
+ 1/*REGUSE*/,
+ DAG, AsmNodeOperands);
break;
}
case InlineAsm::isClobber: {
// Add the clobbered value to the operand list, so that the register
// allocator is aware that the physreg got clobbered.
if (!OpInfo.AssignedRegs.Regs.empty())
- OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
- AsmNodeOperands);
+ OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
+ DAG, AsmNodeOperands);
break;
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 140bad2..c2938e3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1113,7 +1113,8 @@
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
- if ((Flags & 7) != 4 /*MEM*/) {
+ if ((Flags & 7) != 4 /*MEM*/ &&
+ (Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) {
// Just skip over this operand, copying the operands verbatim.
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
i += (Flags >> 3) + 1;
@@ -1128,7 +1129,7 @@
// Add this to the output node.
MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
- Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
+ Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3),
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;