expand tblgen's support for instructions with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98900 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp
index f7960cb..9fd557f 100644
--- a/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1163,12 +1163,14 @@
} else if (!InstInfo.ImplicitDefs.empty()) {
// If the instruction has implicit defs, the first one defines the result
// type.
- assert(InstInfo.ImplicitDefs[0]->isSubClassOf("Register"));
Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
+ assert(FirstImplicitDef->isSubClassOf("Register"));
const std::vector<MVT::SimpleValueType> &RegVTs =
CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
- if (!RegVTs.empty())
+ if (RegVTs.size() == 1)
ResultType = EEVT::TypeSet(RegVTs);
+ else
+ ResultType = EEVT::TypeSet(MVT::isVoid, TP);
} else {
// Otherwise, the instruction produces no value result.
// FIXME: Model "no result" different than "one result that is void"