commit 92a202213bb4c20301abf6ab64e46df3695e60bf
author Owen Anderson <resistor@mac.com> Thu Jul 21 18:54:16 2011 +0000
committer Owen Anderson <resistor@mac.com> Thu Jul 21 18:54:16 2011 +0000
tree ea32134f1f818aa4c39815bf26129c890bff42e9
parent a305fe75450348677a228f7d0f1cc53b2504b562

Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates.  This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 708e88b..3c760f8 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -741,7 +741,8 @@
       MI.eraseFromParent();
       return true;
     }
-    case ARM::MOVCCs: {
+    case ARM::MOVCCsi:
+    case ARM::MOVCCsr: {
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
               (MI.getOperand(1).getReg()))
         .addReg(MI.getOperand(2).getReg(),