Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 452f561..c1be3e9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -644,7 +644,10 @@
!RegisterVT.isInteger() || RegisterVT.isVector() ||
!FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
continue;
-
+
+ if (FuncInfo.PHIDestRegs.count(Regs[Part+i]) && !FuncInfo.AllPredsVisited)
+ continue;
+
const FunctionLoweringInfo::LiveOutInfo &LOI =
FuncInfo.LiveOutRegInfo[Regs[Part+i]];
@@ -6466,6 +6469,9 @@
}
}
+ if (!EnableFastISel)
+ FuncInfo.PHISrcToDestMap[Reg] = FuncInfo.ValueMap[PN];
+
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
SmallVector<EVT, 4> ValueVTs;