Use LiveRangeQuery in ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157144 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 9f8b461..54f3dd3 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -445,19 +445,11 @@
// Lookup this operand's reaching definition.
assert(LIS && "vreg dependencies requires LiveIntervals");
- SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
- LiveInterval *LI = &LIS->getInterval(Reg);
- VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
+ LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
+ VNInfo *VNI = LRQ.valueIn();
- // Special case: An early-clobber tied operand reads and writes the
- // register one slot early. e.g. InlineAsm.
- //
- // FIXME: Same special case is in shrinkToUses. Hide under an API.
- if (SlotIndex::isSameInstr(VNI->def, UseIdx)) {
- UseIdx = VNI->def;
- VNI = LI->getVNInfoBefore(UseIdx);
- }
// VNI will be valid because MachineOperand::readsReg() is checked by caller.
+ assert(VNI && "No value to read by operand");
MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
// Phis and other noninstructions (after coalescing) have a NULL Def.
if (Def) {