Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.
New I just have to move this to a common place :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index ef1c86d..b7e3766 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1287,8 +1287,7 @@
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
}
-SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG,
- const ARMSubtarget *ST) {
+SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
SDOperand ChainOp = Op.getOperand(0);
SDOperand DestOp = Op.getOperand(1);
SDOperand SourceOp = Op.getOperand(2);
@@ -1311,11 +1310,9 @@
// The libc version is likely to be faster for the these cases. It can
// use the address value and run time information about the CPU.
// With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
- // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb. Change
- // this once Thumb ldmia / stmia support is added.
unsigned Size = I->getValue();
if (AlwaysInline ||
- (!ST->isThumb() && Size <= Subtarget->getMaxInlineSizeThreshold() &&
+ (Size <= Subtarget->getMaxInlineSizeThreshold() &&
(Align & 3) == 0))
return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG);
return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG);
@@ -1461,7 +1458,7 @@
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
- case ISD::MEMCPY: return LowerMEMCPY(Op, DAG, Subtarget);
+ case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
}
return SDOperand();
}