commit 95934844e3614adf949b09085be21f41ea4218ce
author Akira Hatanaka <ahatanak@gmail.com> Sat Sep 24 01:34:44 2011 +0000
committer Akira Hatanaka <ahatanak@gmail.com> Sat Sep 24 01:34:44 2011 +0000
tree 92430d9b76dee2f27ea3a4c023728ac172824be8
parent 51f0c7641983469cbd29f8862a121645471a885a

Preparation for adding simple Mips64 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsISelLowering.cpp

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 0c0b9ab..77650c7 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -95,6 +95,9 @@
   addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
   addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
 
+  if (HasMips64)
+    addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
+
   // When dealing with single precision only, use libcalls
   if (!Subtarget->isSingleFloat()) {
     if (HasMips64)
@@ -2260,6 +2263,8 @@
 
       if (RegVT == MVT::i32)
         RC = Mips::CPURegsRegisterClass;
+      else if (RegVT == MVT::i64)
+        RC = Mips::CPU64RegsRegisterClass;
       else if (RegVT == MVT::f32)
         RC = Mips::FGR32RegisterClass;
       else if (RegVT == MVT::f64) {