added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23849 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index bb2162b..e523245 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -697,7 +697,7 @@
Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
(opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::MULHU:
@@ -1084,10 +1084,10 @@
break;
}
case MVT::i16:
- BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
break;
case MVT::i8:
- BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
break;
case MVT::i1:
Tmp2 = MakeReg(MVT::i64);