commit 96f1d8ebdd33b3f9bdb3b1163f36072c68599f42
author Gabor Greif <ggreif@gmail.com> Thu Jul 22 13:36:47 2010 +0000
committer Gabor Greif <ggreif@gmail.com> Thu Jul 22 13:36:47 2010 +0000
tree 86a40f3abd0a781fd38106bc6f9b3137ccab1787
parent 907cd1a569c4b3aa8451ea509f6b1018134884d3

mass elimination of reliance on automatic iterator dereferencing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109103 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 1fb20f1..b26208b 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -94,7 +94,7 @@
          !(I->getOpcode() == Instruction::BitCast ||
            I->getOpcode() == Instruction::PtrToInt ||
            I->getOpcode() == Instruction::IntToPtr) &&
-         cast<Instruction>(I->use_begin())->getParent() == I->getParent();
+         cast<Instruction>(*I->use_begin())->getParent() == I->getParent();
 }
 
 unsigned FastISel::getRegForValue(const Value *V) {