commit 972569a22f4add23e03d750a130ebede99575eb0
author Misha Brukman <brukman+llvm@gmail.com> Fri Jun 25 18:36:53 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Fri Jun 25 18:36:53 2004 +0000
tree 337849f5c3449750bd2c9a04e5dcdef2496378f5
parent f5076133a94a08e385e5dd1b0c75f2d32fe542ab

Fix opcode: no immediate in an `or r1, r2, r3' (all registers) instr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14411 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 6f214f8..a75a4b0 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1052,7 +1052,7 @@
     break;
   case cInt:
     // Move value into target register (32->32)
-    BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
+    BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
     break;
   default:
     assert(0 && "Unpromotable operand class in promote32");