Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index dbeba16..6159628 100644
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -337,7 +337,10 @@
make it run faster:</p>
<ul>
- <li>....</li>
+ <li>TableGen can now synthesize register classes that are only needed to
+ represent combinations of constraints from instructions and sub-registers.
+ The synthetic register classes inherit most of their properties form their
+ closest user-defined super-class.</li>
</ul>
</div>