Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index 63bb8f6..b275d2a 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -15,6 +15,7 @@
#ifndef TARGET_ARM_H
#define TARGET_ARM_H
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
@@ -91,7 +92,8 @@
FunctionPass *createARMISelDag(ARMTargetMachine &TM);
FunctionPass *createARMCodePrinterPass(raw_ostream &O,
ARMTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
MachineCodeEmitter &MCE);
FunctionPass *createARMLoadStoreOptimizationPass();
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index a2ee52e..a5ce86e 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -138,17 +138,20 @@
// Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createARMISelDag(*this));
return false;
}
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
- if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
+ if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
PM.add(createARMLoadStoreOptimizationPass());
- if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
+ if (OptLevel != CodeGenOpt::None &&
+ !DisableIfConversion && !Subtarget.isThumb())
PM.add(createIfConverterPass());
PM.add(createARMConstantIslandPass());
@@ -156,7 +159,7 @@
}
bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
@@ -168,8 +171,10 @@
}
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
if (DefRelocModel == Reloc::Default)
setRelocationModel(Reloc::Static);
@@ -186,7 +191,7 @@
}
bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for ARM.
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index cfb6178..3f65f71 100644
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -41,7 +41,8 @@
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
ARMTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@@ -69,14 +70,17 @@
virtual const TargetAsmInfo *createTargetAsmInfo() const;
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE);
};
/// ThumbTargetMachine - Thumb target machine.
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 6559a9d..d5def37 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -81,7 +81,8 @@
bool InCPMode;
public:
explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
InCPMode(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
@@ -1061,7 +1062,8 @@
///
FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
ARMTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index 994edaa..853109a 100644
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -15,18 +15,20 @@
#ifndef TARGET_ALPHA_H
#define TARGET_ALPHA_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class AlphaTargetMachine;
class FunctionPass;
- class TargetMachine;
class MachineCodeEmitter;
class raw_ostream;
FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
MachineCodeEmitter &MCE);
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index 7a87612..802a803 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -77,25 +77,26 @@
//===----------------------------------------------------------------------===//
bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createAlphaISelDag(*this));
return false;
}
bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer
PM.add(createAlphaBranchSelectionPass());
return false;
}
bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createAlphaLLRPPass(*this));
PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
return false;
}
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
PM.add(createAlphaCodeEmitterPass(*this, MCE));
if (DumpAsm)
@@ -103,7 +104,8 @@
return false;
}
bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel, bool DumpAsm,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
MachineCodeEmitter &MCE) {
return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
}
diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h
index 309c2e8..8dd07db 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.h
+++ b/lib/Target/Alpha/AlphaTargetMachine.h
@@ -58,14 +58,17 @@
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE);
};
} // end namespace llvm
diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
index 292a380..0d200c5 100644
--- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
@@ -37,7 +37,8 @@
///
explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(o, tm, T, OL, V) {}
virtual const char *getPassName() const {
@@ -68,7 +69,7 @@
///
FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index 0a8e9df..5b35580 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -3587,7 +3587,7 @@
bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(createGCLoweringPass());
diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h
index a851486..8b26245 100644
--- a/lib/Target/CBackend/CTargetMachine.h
+++ b/lib/Target/CBackend/CTargetMachine.h
@@ -28,7 +28,7 @@
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but must be requested explicitly on
// llc command line.
diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
index 6e77c87..15cacd1 100644
--- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
@@ -49,7 +49,8 @@
std::set<std::string> FnStubs, GVStubs;
public:
explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V) :
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V) :
AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@@ -288,8 +289,9 @@
DwarfWriter *DW;
MachineModuleInfo *MMI;
public:
- LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
- const TargetAsmInfo *T, bool F, bool V)
+ explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
+ const TargetAsmInfo *T, CodeGenOpt::Level F,
+ bool V)
: SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
@@ -615,6 +617,7 @@
///
FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h
index 5c62bc3..77a062e 100644
--- a/lib/Target/CellSPU/SPU.h
+++ b/lib/Target/CellSPU/SPU.h
@@ -16,6 +16,7 @@
#define LLVM_TARGET_IBMCELLSPU_H
#include "llvm/Support/DataTypes.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
class SPUTargetMachine;
@@ -25,7 +26,8 @@
FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
/*--== Utility functions/predicates/etc used all over the place: --==*/
//! Predicate test for a signed 10-bit value
diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp
index c8cf364..7fa9022 100644
--- a/lib/Target/CellSPU/SPUTargetMachine.cpp
+++ b/lib/Target/CellSPU/SPUTargetMachine.cpp
@@ -81,7 +81,8 @@
//===----------------------------------------------------------------------===//
bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel)
{
// Install an instruction selector.
PM.add(createSPUISelDag(*this));
@@ -89,7 +90,7 @@
}
bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h
index e959e91..cd39203 100644
--- a/lib/Target/CellSPU/SPUTargetMachine.h
+++ b/lib/Target/CellSPU/SPUTargetMachine.h
@@ -83,8 +83,10 @@
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp
index 3d63621..849284e 100644
--- a/lib/Target/CppBackend/CPPBackend.cpp
+++ b/lib/Target/CppBackend/CPPBackend.cpp
@@ -1995,7 +1995,7 @@
bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(new CppWriter(o));
return false;
diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h
index 90b8268..db4bc0e 100644
--- a/lib/Target/CppBackend/CPPTargetMachine.h
+++ b/lib/Target/CppBackend/CPPTargetMachine.h
@@ -30,7 +30,7 @@
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }
diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
index 5fd8811..9cdcd73 100644
--- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
@@ -25,7 +25,6 @@
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/Statistic.h"
@@ -38,7 +37,8 @@
std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
public:
explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@@ -370,7 +370,7 @@
///
FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/IA64/IA64.h b/lib/Target/IA64/IA64.h
index 46c26f0..ec8e3d6 100644
--- a/lib/Target/IA64/IA64.h
+++ b/lib/Target/IA64/IA64.h
@@ -14,6 +14,8 @@
#ifndef TARGET_IA64_H
#define TARGET_IA64_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class IA64TargetMachine;
@@ -37,7 +39,8 @@
///
FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
} // End llvm namespace
diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp
index c472657..878a00a 100644
--- a/lib/Target/IA64/IA64TargetMachine.cpp
+++ b/lib/Target/IA64/IA64TargetMachine.cpp
@@ -72,18 +72,20 @@
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel){
PM.add(createIA64DAGToDAGInstructionSelector(*this));
return false;
}
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Make sure everything is bundled happily
PM.add(createIA64BundlingPass(*this));
return true;
}
bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
diff --git a/lib/Target/IA64/IA64TargetMachine.h b/lib/Target/IA64/IA64TargetMachine.h
index 1fbba02..29d625c 100644
--- a/lib/Target/IA64/IA64TargetMachine.h
+++ b/lib/Target/IA64/IA64TargetMachine.h
@@ -51,9 +51,10 @@
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
} // End llvm namespace
diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 8d9a1ea..e5a1203 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -36,7 +36,7 @@
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1664,7 +1664,7 @@
bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel)
+ CodeGenOpt::Level OptLevel)
{
if (FileType != TargetMachine::AssemblyFile) return true;
MSILWriter* Writer = new MSILWriter(o);
diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
index 6692f2e..fd2ae51 100644
--- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
@@ -50,7 +50,8 @@
const MipsSubtarget *Subtarget;
public:
explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
}
@@ -91,7 +92,8 @@
/// regardless of whether the function is in SSA form.
FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
MipsTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h
index abcb9c4..0accb4e 100644
--- a/lib/Target/Mips/Mips.h
+++ b/lib/Target/Mips/Mips.h
@@ -15,6 +15,8 @@
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class MipsTargetMachine;
class FunctionPass;
@@ -25,7 +27,8 @@
FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
MipsTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for Mips registers. This defines a mapping from
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 69a480d..ef524e3 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -105,7 +105,7 @@
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsISelDag(*this));
return false;
@@ -115,7 +115,7 @@
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
+addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsDelaySlotFillerPass(*this));
return true;
@@ -124,7 +124,7 @@
// Implements the AssemblyEmitter for the target. Must return
// true if AssemblyEmitter is supported
bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out)
{
// Output assembly language.
diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index b5dc058..a9e1df2 100644
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -57,9 +57,12 @@
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h
index 695fe84..42bd7bc 100644
--- a/lib/Target/PIC16/PIC16.h
+++ b/lib/Target/PIC16/PIC16.h
@@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_PIC16_H
#define LLVM_TARGET_PIC16_H
+#include "llvm/Target/TargetMachine.h"
#include <iosfwd>
#include <cassert>
@@ -75,7 +76,8 @@
FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
PIC16TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for PIC16 registers. This defines a mapping from
diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp
index a10fcd4..510e105 100644
--- a/lib/Target/PIC16/PIC16AsmPrinter.cpp
+++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp
@@ -161,7 +161,7 @@
///
FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
PIC16TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/PIC16/PIC16AsmPrinter.h b/lib/Target/PIC16/PIC16AsmPrinter.h
index 67eca1f..227de70 100644
--- a/lib/Target/PIC16/PIC16AsmPrinter.h
+++ b/lib/Target/PIC16/PIC16AsmPrinter.h
@@ -25,7 +25,8 @@
namespace llvm {
struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {
CurBank = "";
FunctionLabelBegin = '@';
diff --git a/lib/Target/PIC16/PIC16TargetMachine.cpp b/lib/Target/PIC16/PIC16TargetMachine.cpp
index adc2120..9c52ee5 100644
--- a/lib/Target/PIC16/PIC16TargetMachine.cpp
+++ b/lib/Target/PIC16/PIC16TargetMachine.cpp
@@ -56,15 +56,15 @@
}
bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPIC16ISelDag(*this));
return false;
}
bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
- raw_ostream &Out) {
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+ bool Verbose, raw_ostream &Out) {
// Output assembly language.
PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
return false;
diff --git a/lib/Target/PIC16/PIC16TargetMachine.h b/lib/Target/PIC16/PIC16TargetMachine.h
index b6b5d31..d960459 100644
--- a/lib/Target/PIC16/PIC16TargetMachine.h
+++ b/lib/Target/PIC16/PIC16TargetMachine.h
@@ -57,8 +57,10 @@
return const_cast<PIC16TargetLowering*>(&TLInfo);
}
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
}; // PIC16TargetMachine.
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index c690982..96c8665 100644
--- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -55,7 +55,8 @@
const PPCSubtarget &Subtarget;
public:
explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V),
Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
@@ -298,7 +299,8 @@
MachineModuleInfo *MMI;
public:
explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
@@ -327,7 +329,8 @@
raw_ostream &OS;
public:
explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
virtual const char *getPassName() const {
@@ -1176,7 +1179,8 @@
///
FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
PPCTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
if (Subtarget->isDarwin()) {
diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index f5507c2..78c970e 100644
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -18,6 +18,8 @@
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class PPCTargetMachine;
class FunctionPass;
@@ -28,7 +30,7 @@
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
PPCTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel, bool Verbose);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
MachineCodeEmitter &MCE);
} // end namespace llvm;
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 3e1dc32..bb17ea9 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -129,21 +129,22 @@
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPPCISelDag(*this));
return false;
}
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
-
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@@ -153,7 +154,8 @@
return false;
}
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
// FIXME: This should be moved to TargetJITInfo!!
@@ -184,7 +186,8 @@
return false;
}
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index 2f839fb..efdf918 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -46,7 +46,8 @@
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
PPCTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@@ -76,13 +77,15 @@
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool getEnableTailMergeDefault() const;
};
diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
index ab18684..115f9b0 100644
--- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
@@ -49,7 +49,8 @@
ValueMapTy NumberForBB;
public:
explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@@ -82,7 +83,7 @@
///
FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 74b2e47..bb03f30 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -15,17 +15,18 @@
#ifndef TARGET_SPARC_H
#define TARGET_SPARC_H
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
class FunctionPass;
- class TargetMachine;
class SparcTargetMachine;
class raw_ostream;
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
} // end namespace llvm;
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index cabfce1..eda0309 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -69,7 +69,7 @@
}
bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createSparcISelDag(*this));
return false;
}
@@ -77,14 +77,15 @@
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel){
PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this));
return true;
}
bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index 927cbb5..40b44f2 100644
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -51,9 +51,10 @@
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
index ecb0f4d..1e8b3ad 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
@@ -34,7 +34,8 @@
const X86Subtarget *Subtarget;
public:
explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
}
diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
index 85c5471..c874849 100644
--- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
@@ -25,7 +25,8 @@
///
FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
if (Subtarget->isFlavorIntel()) {
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
index 054cd9c..9520d98 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
@@ -26,7 +26,8 @@
struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 9dad017..a9ac859 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -15,6 +15,8 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class X86TargetMachine;
@@ -25,7 +27,7 @@
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
@@ -44,7 +46,8 @@
///
FunctionPass *createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 7da43e9..ceac594 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -134,7 +134,7 @@
bool OptForSize;
public:
- explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+ explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(tm, OptLevel),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
@@ -306,7 +306,7 @@
bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == 0) return false;
+ if (OptLevel == CodeGenOpt::None) return false;
if (U == Root)
switch (U->getOpcode()) {
@@ -714,7 +714,7 @@
OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
DEBUG(BB->dump());
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PreprocessForRMW();
// FIXME: This should only happen when not compiled with -O0.
@@ -1744,6 +1744,7 @@
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
+ llvm::CodeGenOpt::Level OptLevel) {
return new X86DAGToDAGISel(TM, OptLevel);
}
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index df086e8..761d098 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -180,7 +180,8 @@
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
@@ -194,20 +195,22 @@
return false;
}
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createX86MaxStackAlignmentCalculatorPass());
return false; // -print-machineinstr shouldn't print after this.
}
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@@ -216,7 +219,8 @@
return false;
}
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -245,7 +249,8 @@
}
bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel, bool DumpAsm,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
MachineCodeEmitter &MCE) {
PM.add(createX86CodeEmitterPass(*this, MCE));
if (DumpAsm) {
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index 4b4e26f..c25fc1d 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -45,7 +45,8 @@
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@@ -74,14 +75,16 @@
}
// Set up the pass pipeline.
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h
index 1c99d88..5722b87 100644
--- a/lib/Target/XCore/XCore.h
+++ b/lib/Target/XCore/XCore.h
@@ -15,6 +15,8 @@
#ifndef TARGET_XCORE_H
#define TARGET_XCORE_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class FunctionPass;
class TargetMachine;
@@ -24,7 +26,8 @@
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
XCoreTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for XCore registers. This defines a mapping from
diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp
index accc35a..45b3c37 100644
--- a/lib/Target/XCore/XCoreAsmPrinter.cpp
+++ b/lib/Target/XCore/XCoreAsmPrinter.cpp
@@ -57,8 +57,9 @@
DwarfWriter *DW;
const XCoreSubtarget &Subtarget;
public:
- XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0),
Subtarget(*TM.getSubtargetImpl()) {}
@@ -105,7 +106,7 @@
///
FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
XCoreTargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp
index bb0ba77..5437c57 100644
--- a/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -56,13 +56,13 @@
}
bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createXCoreISelDag(*this));
return false;
}
bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h
index e57e672..2385aed 100644
--- a/lib/Target/XCore/XCoreTargetMachine.h
+++ b/lib/Target/XCore/XCoreTargetMachine.h
@@ -52,8 +52,9 @@
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};