ARM parsing aliases for VLD1 single register all lanes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 1953dad..0a7e251 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -576,6 +576,7 @@
   REG("VecListThreeD");
   REG("VecListFourD");
   REG("VecListTwoQ");
+  REG("VecListOneDAllLanes");
 
   IMM("i32imm");
   IMM("i32imm_hilo16");