commit 98f213cd60f21437846ce4075c0fe15d7f09a3fd
author Kevin Enderby <enderby@apple.com> Fri Sep 02 18:03:03 2011 +0000
committer Kevin Enderby <enderby@apple.com> Fri Sep 02 18:03:03 2011 +0000
tree 38e5fe7d9fdc0ad2dce3889538fbd3081af9b8ad
parent ca52a7e38c0bcdd1a8f32212239606fe1f5e3152

Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 1b37aa8..5f8fe6e 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -225,7 +225,8 @@
   
   Operands = &insn.Operands.OperandList;
   
-  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
+  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
+                     (Name.find("CRC32") != Name.npos);
   HasFROperands    = hasFROperands();
   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
   
@@ -318,7 +319,9 @@
     else
       insnContext = IC_64BIT;
   } else {
-    if (HasOpSizePrefix)
+    if (HasOpSizePrefix && Prefix == X86Local::TF)
+      insnContext = IC_XD;
+    else if (HasOpSizePrefix)
       insnContext = IC_OPSIZE;
     else if (Prefix == X86Local::XD)
       insnContext = IC_XD;