Add new immed16.ll test case, fix CellSPU errata to make test case work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45196 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index ba406f4..a036038 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -597,7 +597,7 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
- DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
+ DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
CurDAG->getTargetConstant(0, MVT::i32));
} else if (Opc == SPUISD::LDRESULT) {
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index d7091eb..253fafb 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -670,6 +670,11 @@
SDOperand ptrOp;
int offset;
+ if (basep.getOpcode() == ISD::FrameIndex) {
+ // FrameIndex nodes are always properly aligned. Really.
+ return SDOperand();
+ }
+
if (basep.getOpcode() == ISD::ADD) {
const ConstantSDNode *CN = cast<ConstantSDNode>(basep.Val->getOperand(1));
assert(CN != NULL
@@ -694,13 +699,10 @@
stVecVT = MVT::v16i8;
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
- // Realign the pointer as a D-Form address (ptrOp is the pointer,
- // to force a register load with the address; basep is the actual
- // dform addr offs($reg).
- ptrOp = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
- DAG.getConstant(0, PtrVT));
- basep = DAG.getNode(SPUISD::DFormAddr, PtrVT,
- ptrOp, DAG.getConstant((offset & ~0xf), PtrVT));
+ // Realign the pointer as a D-Form address (ptrOp is the pointer, basep is
+ // the actual dform addr offs($reg).
+ basep = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
+ DAG.getConstant((offset & ~0xf), PtrVT));
// Create the 16-byte aligned vector load
SDOperand alignLoad =
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 5846aad..efd45f5 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -62,7 +62,6 @@
case SPU::AHIvec:
case SPU::AHIr16:
case SPU::AIvec:
- case SPU::AIr32:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@@ -74,6 +73,19 @@
return true;
}
break;
+ case SPU::AIr32:
+ assert(MI.getNumOperands() == 3 &&
+ "wrong number of operands to AIr32");
+ if (MI.getOperand(0).isRegister() &&
+ (MI.getOperand(1).isRegister() ||
+ MI.getOperand(1).isFrameIndex()) &&
+ (MI.getOperand(2).isImmediate() &&
+ MI.getOperand(2).getImmedValue() == 0)) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ break;
#if 0
case SPU::ORIf64:
case SPU::ORIf32:
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 792041e..82e0a93 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -3476,10 +3476,8 @@
// Force load of global address to a register. These forms show up in
// SPUISD::DFormAddr pseudo instructions:
-/*
def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
- */
// Instrinsics:
include "CellSDKIntrinsics.td"
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 7822d1e..26917fe 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -585,8 +585,6 @@
SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
RegScavenger *RS) const
{
- assert(SPAdj == 0 && "Unexpected SP adjacency == 0");
-
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();