diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 49b695c..f1871fc 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2730,7 +2730,7 @@
       SDNode *User = *UI;
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue UseOp = User->getOperand(i);
-        if (UseOp.Val == N && UseOp.ResNo == 0) {
+        if (UseOp.Val == N && UseOp.getResNo() == 0) {
           BothLiveOut = true;
           break;
         }
@@ -3366,7 +3366,7 @@
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
     return Elt.Val;
-  return Elt.getOperand(Elt.ResNo).Val;
+  return Elt.getOperand(Elt.getResNo()).Val;
 }
 
 /// CombineConsecutiveLoads - build_pair (load, load) -> load
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index e5a1f57..f779894 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -821,7 +821,7 @@
 
       for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
         AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
-      return Result.getValue(Op.ResNo);
+      return Result.getValue(Op.getResNo());
     }
     // Otherwise this is an unhandled builtin node.  splat.
 #ifndef NDEBUG
@@ -901,7 +901,7 @@
     Tmp2 = LegalizeOp(Result.getValue(1));
     AddLegalizedOperand(Op.getValue(0), Tmp1);
     AddLegalizedOperand(Op.getValue(1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   case ISD::EHSELECTION: {
     Tmp1 = LegalizeOp(Node->getOperand(0));
     Tmp2 = LegalizeOp(Node->getOperand(1));
@@ -935,7 +935,7 @@
     Tmp2 = LegalizeOp(Result.getValue(1));
     AddLegalizedOperand(Op.getValue(0), Tmp1);
     AddLegalizedOperand(Op.getValue(1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   case ISD::EH_RETURN: {
     MVT VT = Node->getValueType(0);
     // The only "good" option for this node is to custom lower it.
@@ -959,7 +959,7 @@
     break;
   case ISD::MERGE_VALUES:
     // Legalize eliminates MERGE_VALUES nodes.
-    Result = Node->getOperand(Op.ResNo);
+    Result = Node->getOperand(Op.getResNo());
     break;
   case ISD::CopyFromReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));
@@ -980,7 +980,7 @@
     // legalized both of them.
     AddLegalizedOperand(Op.getValue(0), Result);
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   case ISD::UNDEF: {
     MVT VT = Op.getValueType();
     switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
@@ -1025,7 +1025,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }    
 
   case ISD::DBG_STOPPOINT:
@@ -1199,7 +1199,7 @@
     }
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::ATOMIC_LOAD_ADD:
   case ISD::ATOMIC_LOAD_SUB:
@@ -1232,7 +1232,7 @@
     }
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::Constant: {
     ConstantSDNode *CN = cast<ConstantSDNode>(Node);
@@ -1331,7 +1331,7 @@
       if (Tmp3.Val->getValueType(i) == MVT::Flag)
         continue;
       Tmp1 = LegalizeOp(Tmp3.getValue(i));
-      if (Op.ResNo == i)
+      if (Op.getResNo() == i)
         Tmp2 = Tmp1;
       AddLegalizedOperand(SDValue(Node, i), Tmp1);
     }
@@ -1625,7 +1625,7 @@
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     if (Node->getNumValues() == 2)
       AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   case ISD::DYNAMIC_STACKALLOC: {
     MVT VT = Node->getValueType(0);
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -1684,7 +1684,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Tmp1);
     AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
   }
   case ISD::INLINEASM: {
     SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
@@ -1720,7 +1720,7 @@
     // INLINE asm returns a chain and flag, make sure to add both to the map.
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
   case ISD::BR:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -1935,7 +1935,7 @@
       // legalized both of them.
       AddLegalizedOperand(SDValue(Node, 0), Tmp3);
       AddLegalizedOperand(SDValue(Node, 1), Tmp4);
-      return Op.ResNo ? Tmp4 : Tmp3;
+      return Op.getResNo() ? Tmp4 : Tmp3;
     } else {
       MVT SrcVT = LD->getMemoryVT();
       unsigned SrcWidth = SrcVT.getSizeInBits();
@@ -2124,7 +2124,7 @@
       // both of them.
       AddLegalizedOperand(SDValue(Node, 0), Tmp1);
       AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-      return Op.ResNo ? Tmp2 : Tmp1;
+      return Op.getResNo() ? Tmp2 : Tmp1;
     }
   }
   case ISD::EXTRACT_ELEMENT: {
@@ -2215,7 +2215,7 @@
           Result = LegalizeOp(Result);
         } else {
           SDNode *InVal = Tmp2.Val;
-          int InIx = Tmp2.ResNo;
+          int InIx = Tmp2.getResNo();
           unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
           MVT EVT = InVal->getValueType(InIx).getVectorElementType();
           
@@ -2411,7 +2411,7 @@
         // in the high half of the vector.
         if (ST->getValue().getValueType().isVector()) {
           SDNode *InVal = ST->getValue().Val;
-          int InIx = ST->getValue().ResNo;
+          int InIx = ST->getValue().getResNo();
           MVT InVT = InVal->getValueType(InIx);
           unsigned NumElems = InVT.getVectorNumElements();
           MVT EVT = InVT.getVectorElementType();
@@ -2619,7 +2619,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Tmp1);
     AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.ResNo ? Tmp2 : Tmp1;
+    return Op.getResNo() ? Tmp2 : Tmp1;
 
   case ISD::STACKRESTORE:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -2875,7 +2875,7 @@
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           Tmp2 = LegalizeOp(Tmp1.getValue(i));
           AddLegalizedOperand(SDValue(Node, i), Tmp2);
-          if (i == Op.ResNo)
+          if (i == Op.getResNo())
             RetVal = Tmp2;
         }
         assert(RetVal.Val && "Illegal result number");
@@ -2888,7 +2888,7 @@
     // legalized all of them.
     for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
       AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
-    return Result.getValue(Op.ResNo);
+    return Result.getValue(Op.getResNo());
   }
 
     // Binary operators
@@ -3278,7 +3278,7 @@
     // legalized both of them.
     AddLegalizedOperand(SDValue(Node, 0), Result);
     AddLegalizedOperand(SDValue(Node, 1), Tmp1);
-    return Op.ResNo ? Tmp1 : Result;
+    return Op.getResNo() ? Tmp1 : Result;
   }
     
   case ISD::VACOPY: 
@@ -3574,7 +3574,7 @@
       // The input has to be a vector type, we have to either scalarize it, pack
       // it, or convert it based on whether the input vector type is legal.
       SDNode *InVal = Node->getOperand(0).Val;
-      int InIx = Node->getOperand(0).ResNo;
+      int InIx = Node->getOperand(0).getResNo();
       unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
       MVT EVT = InVal->getValueType(InIx).getVectorElementType();
     
@@ -3876,7 +3876,7 @@
     Result = LegalizeOp(Result);
     AddLegalizedOperand(SDValue(Node, 0), Result);
     AddLegalizedOperand(SDValue(Node, 1), Tmp1);
-    return Op.ResNo ? Tmp1 : Result;
+    return Op.getResNo() ? Tmp1 : Result;
   }
   case ISD::FLT_ROUNDS_: {
     MVT VT = Node->getValueType(0);
@@ -5808,7 +5808,7 @@
       break;
     }
     // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
-    assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
+    assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
            Op.getValue(1).getValueType() == MVT::Other &&
            "unhandled MERGE_VALUES");
     ExpandOp(Op.getOperand(0), Lo, Hi);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3b2265e..d0a94d1 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -62,7 +62,7 @@
   if (TargetRegisterInfo::isVirtualRegister(Reg))
     return;
 
-  unsigned ResNo = User->getOperand(2).ResNo;
+  unsigned ResNo = User->getOperand(2).getResNo();
   if (Def->isMachineOpcode()) {
     const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
     if (ResNo >= II.getNumDefs() &&
@@ -430,7 +430,7 @@
     bool Match = true;
     if (User->getOpcode() == ISD::CopyToReg && 
         User->getOperand(2).Val == Node &&
-        User->getOperand(2).ResNo == ResNo) {
+        User->getOperand(2).getResNo() == ResNo) {
       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
         VRBase = DestReg;
@@ -440,9 +440,9 @@
     } else {
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue Op = User->getOperand(i);
-        if (Op.Val != Node || Op.ResNo != ResNo)
+        if (Op.Val != Node || Op.getResNo() != ResNo)
           continue;
-        MVT VT = Node->getValueType(Op.ResNo);
+        MVT VT = Node->getValueType(Op.getResNo());
         if (VT != MVT::Other && VT != MVT::Flag)
           Match = false;
       }
@@ -490,7 +490,7 @@
   SDNode *User = *Node->use_begin();
   if (User->getOpcode() == ISD::CopyToReg && 
       User->getOperand(2).Val == Node &&
-      User->getOperand(2).ResNo == ResNo) {
+      User->getOperand(2).getResNo() == ResNo) {
     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       return Reg;
@@ -514,7 +514,7 @@
       SDNode *User = *UI;
       if (User->getOpcode() == ISD::CopyToReg && 
           User->getOperand(2).Val == Node &&
-          User->getOperand(2).ResNo == i) {
+          User->getOperand(2).getResNo() == i) {
         unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
         if (TargetRegisterInfo::isVirtualRegister(Reg)) {
           VRBase = Reg;
@@ -547,7 +547,7 @@
   if (Op.isMachineOpcode() &&
       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
     // Add an IMPLICIT_DEF instruction before every use.
-    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.ResNo);
+    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
     // does not include operand register class info.
     if (!VReg) {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index be07f56..cd29cf1 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -652,7 +652,7 @@
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
-    MVT VT = Op.Val->getValueType(Op.ResNo);
+    MVT VT = Op.Val->getValueType(Op.getResNo());
     if (VT == MVT::Flag)
       return NULL;
   }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 640fc97..5c996a0 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -327,7 +327,7 @@
                               const SDValue *Ops, unsigned NumOps) {
   for (; NumOps; --NumOps, ++Ops) {
     ID.AddPointer(Ops->Val);
-    ID.AddInteger(Ops->ResNo);
+    ID.AddInteger(Ops->getResNo());
   }
 }
 
@@ -337,7 +337,7 @@
                               const SDUse *Ops, unsigned NumOps) {
   for (; NumOps; --NumOps, ++Ops) {
     ID.AddPointer(Ops->getVal());
-    ID.AddInteger(Ops->getSDValue().ResNo);
+    ID.AddInteger(Ops->getSDValue().getResNo());
   }
 }
 
@@ -3666,7 +3666,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -3695,7 +3695,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -3761,7 +3761,7 @@
   // See if the modified node already exists.
   void *InsertPos = 0;
   if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
-    return SDValue(Existing, InN.ResNo);
+    return SDValue(Existing, InN.getResNo());
   
   // Nope it doesn't.  Remove the node from its current place in the maps.
   if (InsertPos)
@@ -4161,7 +4161,7 @@
 void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
                                       DAGUpdateListener *UpdateListener) {
   SDNode *From = FromN.Val;
-  assert(From->getNumValues() == 1 && FromN.ResNo == 0 && 
+  assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 
          "Cannot replace with this method!");
   assert(From != To.Val && "Cannot replace uses of with self");
 
@@ -4267,7 +4267,7 @@
     for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
          I != E; ++I, ++operandNum)
       if (I->getVal() == From) {
-        const SDValue &ToOp = To[I->getSDValue().ResNo];
+        const SDValue &ToOp = To[I->getSDValue().getResNo()];
         From->removeUser(operandNum, U);
         *I = ToOp;
         I->setUser(U);
@@ -4573,7 +4573,7 @@
 
   // TODO: Only iterate over uses of a given value of the node
   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
-    if (UI.getUse().getSDValue().ResNo == Value) {
+    if (UI.getUse().getSDValue().getResNo() == Value) {
       if (NUses == 0)
         return false;
       --NUses;
@@ -4591,7 +4591,7 @@
   assert(Value < getNumValues() && "Bad value!");
 
   for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
-    if (UI.getUse().getSDValue().ResNo == Value)
+    if (UI.getUse().getSDValue().getResNo() == Value)
       return true;
 
   return false;
@@ -5000,7 +5000,7 @@
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i) OS << ", ";
     OS << (void*)getOperand(i).Val;
-    if (unsigned RN = getOperand(i).ResNo)
+    if (unsigned RN = getOperand(i).getResNo())
       OS << ":" << RN;
   }
 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f35c8d8..35f7909 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1306,7 +1306,7 @@
       else if (F->paramHasAttr(0, ParamAttr::ZExt))
         ExtendKind = ISD::ZERO_EXTEND;
 
-      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
+      getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
                      &Parts[0], NumParts, PartVT, ExtendKind);
 
       for (unsigned i = 0; i < NumParts; ++i) {
@@ -2736,15 +2736,15 @@
   // Copy the beginning value(s) from the original aggregate.
   for (; i != LinearIndex; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.ResNo + i);
+                SDValue(Agg.Val, Agg.getResNo() + i);
   // Copy values from the inserted value(s).
   for (; i != LinearIndex + NumValValues; ++i)
     Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Val.Val, Val.ResNo + i - LinearIndex);
+                SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
   // Copy remaining value(s) from the original aggregate.
   for (; i != NumAggValues; ++i)
     Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
-                SDValue(Agg.Val, Agg.ResNo + i);
+                SDValue(Agg.Val, Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
                                   &Values[0], NumAggValues));
@@ -2769,8 +2769,8 @@
   // Copy out the selected value(s).
   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
     Values[i - LinearIndex] =
-      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
-                   SDValue(Agg.Val, Agg.ResNo + i);
+      OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.getResNo() + i)) :
+                   SDValue(Agg.Val, Agg.getResNo() + i);
 
   setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
                                   &Values[0], NumValValues));
@@ -2965,7 +2965,7 @@
   bool isVolatile = I.isVolatile();
   unsigned Alignment = I.getAlignment();
   for (unsigned i = 0; i != NumValues; ++i)
-    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
+    Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo() + i),
                              DAG.getNode(ISD::ADD, PtrVT, Ptr,
                                          DAG.getConstant(Offsets[i], PtrVT)),
                              PtrV, Offsets[i],
@@ -3810,7 +3810,7 @@
     unsigned NumParts = TLI->getNumRegisters(ValueVT);
     MVT RegisterVT = RegVTs[Value];
 
-    getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
+    getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
                    &Parts[Part], NumParts, RegisterVT);
     Part += NumParts;
   }
@@ -4763,7 +4763,7 @@
          Value != NumValues; ++Value) {
       MVT VT = ValueVTs[Value];
       const Type *ArgTy = VT.getTypeForMVT();
-      SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
+      SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.getResNo() + Value);
       ISD::ArgFlagsTy Flags;
       unsigned OriginalAlignment =
         getTargetData()->getABITypeAlignment(ArgTy);
@@ -5017,8 +5017,8 @@
       (Op.getOpcode() == ISD::LOAD &&
        IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
       (Op.getOpcode() == ISD::MERGE_VALUES &&
-       Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
-       IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
+       Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
+       IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
                                        getOperand(1))))
     return true;
   return false;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 34a3101..990308f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -59,7 +59,7 @@
     static EdgeIter getEdgeTarget(const void *Node, EdgeIter I) {
       SDNode *TargetNode = *I;
       SDNodeIterator NI = SDNodeIterator::begin(TargetNode);
-      std::advance(NI, I.getNode()->getOperand(I.getOperand()).ResNo);
+      std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo());
       return NI;
     }
 
@@ -110,7 +110,7 @@
                                        GraphWriter<SelectionDAG*> &GW) {
       GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
       if (G->getRoot().Val)
-        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().ResNo,
+        GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().getResNo(),
                     "color=blue,style=dashed");
     }
   };