Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 056c540..e220b08 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -271,7 +271,7 @@
if (!Modifier || strcmp(Modifier, "no_hash") != 0)
O << "#";
- O << (int)MO.getImmedValue();
+ O << (int)MO.getImm();
break;
}
case MachineOperand::MO_MachineBasicBlock:
@@ -351,7 +351,7 @@
void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
- printSOImm(O, MO.getImmedValue(), TAI);
+ printSOImm(O, MO.getImm(), TAI);
}
/// printSOImm2PartOperand - SOImm is broken into two pieces using a mov
@@ -359,8 +359,8 @@
void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
- unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImmedValue());
- unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImmedValue());
+ unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
+ unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
O << "\n\torr";
printPredicateOperand(MI, 2);
@@ -387,7 +387,7 @@
// Print the shift opc.
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
<< " ";
if (MO2.getReg()) {
@@ -426,7 +426,7 @@
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
<< " #" << ShImm;
O << "]";
}
@@ -449,7 +449,7 @@
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
<< " #" << ShImm;
}
@@ -617,7 +617,7 @@
}
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImmedValue();
+ ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImm();
if (CC != ARMCC::AL)
O << ARMCondCodeToString(CC);
}
@@ -631,7 +631,7 @@
}
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int opNum) {
- int Id = (int)MI->getOperand(opNum).getImmedValue();
+ int Id = (int)MI->getOperand(opNum).getImm();
O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
}
@@ -677,7 +677,7 @@
const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
unsigned JTI = MO1.getJumpTableIndex();
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_' << JTI << '_' << MO2.getImmedValue() << ":\n";
+ << '_' << JTI << '_' << MO2.getImm() << ":\n";
const char *JTEntryDirective = TAI->getJumpTableDirective();
if (!JTEntryDirective)
@@ -692,19 +692,19 @@
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
MachineBasicBlock *MBB = JTBBs[i];
if (UseSet && JTSets.insert(MBB).second)
- printPICJumpTableSetLabel(JTI, MO2.getImmedValue(), MBB);
+ printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
O << JTEntryDirective << ' ';
if (UseSet)
O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
- << '_' << JTI << '_' << MO2.getImmedValue()
+ << '_' << JTI << '_' << MO2.getImm()
<< "_set_" << MBB->getNumber();
else if (TM.getRelocationModel() == Reloc::PIC_) {
printBasicBlockLabel(MBB, false, false);
// If the arch uses custom Jump Table directives, don't calc relative to JT
if (!TAI->getJumpTableDirective())
O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
- << getFunctionNumber() << '_' << JTI << '_' << MO2.getImmedValue();
+ << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
} else
printBasicBlockLabel(MBB, false, false);
if (i != e-1)
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 97df9e6..479152b 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -111,7 +111,7 @@
/// machine operand.
int Emitter::getShiftOp(const MachineOperand &MO) {
unsigned ShiftOp = 0x0;
- switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
+ switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr:
ShiftOp = 0X2;
@@ -137,7 +137,7 @@
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
} else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
+ rv = MO.getImm();
} else if (MO.isGlobalAddress()) {
emitGlobalAddressForCall(MO.getGlobal(), false);
} else if (MO.isExternalSymbol()) {
@@ -412,7 +412,7 @@
Value |= 1 << ARMII::I_BitShift;
// set immed_8 field
const MachineOperand &MO = MI.getOperand(OperandIndex);
- op = ARM_AM::getSOImmVal(MO.getImmedValue());
+ op = ARM_AM::getSOImmVal(MO.getImm());
Value |= op;
break;
@@ -441,7 +441,7 @@
// LSR - 011 if it is in register shifts encoding; 010, otherwise.
// ROR - 111 if it is in register shifts encoding; 110, otherwise.
// RRX - 110 and bit[11:7] clear.
- switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
+ switch(ARM_AM::getSORegShOp(MO2.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: {
if(IsShiftByRegister)
@@ -475,7 +475,7 @@
}
}
// set the field related to shift operations (except rrx).
- if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
+ if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
if(IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 9aced30..2dc5bff 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1188,7 +1188,7 @@
// bge L2
// b L1
// L2:
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
+ ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
CC = ARMCC::getOppositeCondition(CC);
unsigned CCReg = MI->getOperand(2).getReg();
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 40a547e..7e08bbc 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -70,7 +70,7 @@
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
- MI->getOperand(3).getImmedValue() == 0) {
+ MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -79,7 +79,7 @@
case ARM::FLDS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -87,7 +87,7 @@
case ARM::tRestore:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -104,7 +104,7 @@
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
- MI->getOperand(3).getImmedValue() == 0) {
+ MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -113,7 +113,7 @@
case ARM::FSTS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -121,7 +121,7 @@
case ARM::tSpill:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -461,7 +461,7 @@
bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
- return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
+ return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
@@ -477,7 +477,7 @@
int PIdx = MI->findFirstPredOperandIdx();
if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx);
- PMO.setImm(Pred[0].getImmedValue());
+ PMO.setImm(Pred[0].getImm());
MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
return true;
}
@@ -490,8 +490,8 @@
if (Pred1.size() > 2 || Pred2.size() > 2)
return false;
- ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
- ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
+ ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
+ ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
if (CC1 == CC2)
return true;
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index b30bdde..d522613 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -255,7 +255,7 @@
}
PredReg = MI->getOperand(PIdx+1).getReg();
- return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
+ return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
}
static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 301a829..afab3d9 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -321,8 +321,8 @@
const MachineInstr *Orig) const {
if (Orig->getOpcode() == ARM::MOVi2pieces) {
emitLoadConstPool(MBB, I, DestReg,
- Orig->getOperand(1).getImmedValue(),
- (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
+ Orig->getOperand(1).getImm(),
+ (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
Orig->getOperand(3).getReg(),
TII, false);
return;
@@ -360,7 +360,7 @@
if (MI->getOperand(4).getReg() == ARM::CPSR)
// If it is updating CPSR, then it cannot be foled.
break;
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -392,7 +392,7 @@
break;
}
case ARM::FCPYS: {
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -406,7 +406,7 @@
break;
}
case ARM::FCPYD: {
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -792,7 +792,7 @@
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
// ADJCALLSTACKUP -> add, sp, sp, amount
MachineInstr *Old = I;
- unsigned Amount = Old->getOperand(0).getImmedValue();
+ unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
// We need to keep the stack aligned properly. To do this, we round the
@@ -805,7 +805,7 @@
unsigned Opc = Old->getOpcode();
bool isThumb = AFI->isThumbFunction();
ARMCC::CondCodes Pred = isThumb
- ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
+ ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
@@ -1160,7 +1160,7 @@
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
- ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
+ ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, Pred, PredReg, TII);