Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 0e901a0..e15f04e 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -374,9 +374,9 @@
case MachineOperand::MO_Immediate:
if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
(MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
- O << (unsigned short int)MO.getImmedValue();
+ O << (unsigned short int)MO.getImm();
else
- O << (short int)MO.getImmedValue();
+ O << (short int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index c3c4ef4..bb8a5c6 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -25,7 +25,7 @@
TM(tm), RI(*this) {}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImmedValue() == 0;
+ return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 5220f59..c04b4c7 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -109,7 +109,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -140,7 +140,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}