| commit | 9a508ef64a194f0f4a3362c55a6e33bec18b7554 | [log] [tgz] |
|---|---|---|
| author | Michael Liao <michael.liao@intel.com> | Wed Jun 05 18:12:26 2013 +0000 |
| committer | Michael Liao <michael.liao@intel.com> | Wed Jun 05 18:12:26 2013 +0000 |
| tree | 6bfbf25677071a5f26b10630d09ac4bb6ba67f63 | |
| parent | bcb1ea8ef62fba49d0e634e1943f829687323314 [diff] [blame] |
[PATCH] Fix VGATHER* operand constraints Add earlyclobber constaints to prevent input register being allocated as the output register because, according to Intel spec [1], "If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault." --- [1] http://software.intel.com/sites/default/files/319433-014.pdf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 02f5fe4..14ec2dd 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2041,6 +2041,8 @@ case Intrinsic::x86_avx2_gather_d_d_256: case Intrinsic::x86_avx2_gather_q_d: case Intrinsic::x86_avx2_gather_q_d_256: { + if (!Subtarget->hasAVX2()) + break; unsigned Opc; switch (IntNo) { default: llvm_unreachable("Impossible intrinsic");