Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
Now Hexagon and SystemZ are not happy with it :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193677 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8237ef3..de0f6ce 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4346,28 +4346,6 @@
}
}
- // Treat SETCC as a vector mask and promote the result type based on the
- // targets expected SETCC result type. This will ensure that SETCC and VSELECT
- // are both split by the type legalizer. This is done to prevent the type
- // legalizer from unrolling SETCC into scalar comparions.
- EVT SelectVT = N->getValueType(0);
- EVT MaskVT = getSetCCResultType(SelectVT);
- if (N0.getOpcode() == ISD::SETCC && N0.getValueType() != MaskVT) {
- SDLoc MaskDL(N0);
-
- // Extend the mask to the desired value type.
- ISD::NodeType ExtendCode =
- TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
- SDValue Mask = DAG.getNode(ExtendCode, MaskDL, MaskVT, N0);
-
- AddToWorkList(Mask.getNode());
-
- SDValue LHS = N->getOperand(1);
- SDValue RHS = N->getOperand(2);
-
- return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS);
- }
-
return SDValue();
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index f1b06fc..7b1d14d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -492,19 +492,14 @@
SDValue Cond = N->getOperand(0);
CL = CH = Cond;
if (Cond.getValueType().isVector()) {
- if (Cond.getOpcode() == ISD::SETCC) {
- assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) &&
- "Condition has not been prepared for split!");
- GetSplitVector(Cond, CL, CH);
- } else {
- EVT ETy = Cond.getValueType().getVectorElementType();
- unsigned NumElements = Cond.getValueType().getVectorNumElements();
- EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), ETy, NumElements / 2);
- CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
- DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
- }
+ assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
+ "Condition legalized before result?");
+ unsigned NumElements = Cond.getValueType().getVectorNumElements();
+ EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
+ CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+ DAG.getConstant(0, TLI.getVectorIdxTy()));
+ CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+ DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
}
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 18064fc..5dbef0f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1546,16 +1546,7 @@
}
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
- if (!VT.isVector())
- return MVT::i8;
-
- const TargetMachine &TM = getTargetMachine();
- if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
- switch(VT.getVectorNumElements()) {
- case 8: return MVT::v8i1;
- case 16: return MVT::v16i1;
- }
-
+ if (!VT.isVector()) return MVT::i8;
return VT.changeVectorElementTypeToInteger();
}