get def use info more correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index c9b1141..2709fc8 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -809,7 +809,7 @@
[(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isSimpleLoad = 1, isReMaterializable = 1 in
+let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr", []>;
@@ -831,6 +831,7 @@
"ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
+let mayLoad = 1 in {
// Load doubleword
def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "d $dst, $addr",
@@ -876,6 +877,7 @@
def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
+}
// Store
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
@@ -939,6 +941,7 @@
//
// FIXME: $dst1 should be a def.
+let mayLoad = 1 in
def LDM : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 8f9bc43..d6fa76c 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -265,7 +265,7 @@
// Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
-let isSimpleLoad = 1 in
+let isSimpleLoad = 1, mayLoad = 1 in
def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr", []>;
@@ -276,7 +276,7 @@
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isSimpleLoad = 1, isReMaterializable = 1 in
+let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>;
@@ -309,6 +309,7 @@
// TODO: A7-44: LDMIA - load multiple
+let mayLoad = 1 in
def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 365ca94..ea87889 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -110,6 +110,7 @@
// Load / store multiple Instructions.
//
+let mayLoad = 1 in {
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops),
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
@@ -119,6 +120,7 @@
variable_ops),
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
+}
let mayStore = 1 in {
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index db39644..5aaed81 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -24,7 +24,7 @@
def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
-def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
+def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>;
def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 7b69d28..fe7b589 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -120,7 +120,8 @@
def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
[SDNPHasChain, SDNPOptInFlag]>;
-def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
+def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
+ [SDNPHasChain, SDNPMayLoad]>;
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
[SDNPHasChain, SDNPMayStore]>;
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index 52f1409..5449e64 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -36,13 +36,13 @@
def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
[SDNPHasChain, SDNPOutFlag]>;
def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
- [SDNPHasChain]>;
+ [SDNPHasChain, SDNPMayLoad]>;
def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
- [SDNPHasChain, SDNPInFlag]>;
+ [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
- [SDNPHasChain]>;
+ [SDNPHasChain, SDNPMayLoad]>;
def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
- [SDNPHasChain, SDNPOutFlag]>;
+ [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
[SDNPHasChain]>;
def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 616fc52..8d8893c 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -86,9 +86,10 @@
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
- [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
- [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
+ SDNPMayLoad]>;
def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
[SDNPHasChain, SDNPOutFlag]>;