commit 9b82425cb0105fd5704f6b9bcd5e7693b05b1759
author Evan Cheng <evan.cheng@apple.com> Fri Nov 20 02:10:27 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Nov 20 02:10:27 2009 +0000
tree 71ae23f126389c602b32c462d679511367f95c9c
parent 2e7e94826a4cf6715b4c07d779fb84994c0bc47b

Also CSE non-pic load from constant pools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index b50b609..33a96f6 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -978,7 +978,10 @@
                                   const MachineInstr *MI1,
                                   const MachineRegisterInfo *MRI) const {
   int Opcode = MI0->getOpcode();
-  if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
+  if (Opcode == ARM::t2LDRpci ||
+      Opcode == ARM::t2LDRpci_pic ||
+      Opcode == ARM::tLDRpci ||
+      Opcode == ARM::tLDRpci_pic) {
     if (MI1->getOpcode() != Opcode)
       return false;
     if (MI0->getNumOperands() != MI1->getNumOperands())